An efficient networking chip appears to be the need of the hour as AI data centers rapidly fill up with a giga-ton of ASICs, GPUs, and orchestration-oriented CPUs. As such, it is hardly a surprise that Google now appears to have tapped Marvell to design a custom networking chip for its TPUs on one of Intel's advanced node processes. Google is tackling the data latency conundrum head-on by tapping Marvell to design a custom networking chip for its TPUs on Intel's advanced lithography For the benefit of those who might not be aware, a networking chip links individual ASICs to […]

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