Samsung has reportedly achieved a 3D transistor design milestone, which could reshape and improve future chip performance. The company continues to expand its technological footprint, along with nurturing the Foundry and LSI divisions.

According to ZDNet (via SemiconductorsX), Samsung walked away from VLSI 2026 with the Best Paper award after presenting a 3D Stacked FET design that squeezes more transistors into less space than anything the industry has managed before.

Samsung’s design piles transistors on top of each other, slashing the footprint in half and theoretically doubling density in a single architectural move.

The score was 8.29 out of 10 across a pool of over 1,000 submissions. The company also pushed the gate pitch, the horizontal width of each transistor, down to 42nm from 48nm.

Samsung’s own V-NAND flash and HBM memory both live in three dimensions. The company’s Foundry business has taken serious hits over the past two years.

Yield problems, lost clients, and a general sense that the gap between Samsung and TSMC was widening rather than closing. A Best Paper at VLSI doesn’t fix a fab, but it signals that the engineering talent is still in the building.

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Samsung is quietly gearing up for the next big step in memory technology. According to recent reports (via @SemiconductorsX), the company is working with partners to introduce equipment for its 7th-generation 10nm-class DRAM, called “1d,” with mass production targeted for late 2027.

Right now, Samsung’s latest is the 1c (6th-gen) process at around 11-12nm. The new 1d shrinks that to about 10-11nm. Smaller lines mean better performance, lower power use, and higher density – exactly what AI systems need.

The company has already been testing samples internally. The current plan is to bring in the new equipment in the first half of 2027 and start real production toward the end of the year.

Why does this matter?

This 1d DRAM is expected to become the core die for HBM5E – Samsung’s high-bandwidth memory planned for 2029. HBM is the super-fast memory that powers AI training and inference in data centers. This stronger manufacturing process will help Samsung remain competitive with SK Hynix in the booming AI memory market.

For everyday users, this new tech will eventually reach phones, laptops, and servers, bringing better speed and lower power use. For the industry, it proves Samsung is still pushing hard on shrinking memory nodes, even as the overall memory market heats up.

It’s a steady, long-term play. No sudden big breakthrough, but these small improvements are exactly what help build real leadership in the AI memory race. We will keep an eye on updates by the end of this year.

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Samsung has reportedly built a data-sharing ecosystem called DSEP, the Data Sharing Eco Platform, and it’s now pulling in more than 60 chip equipment and materials partners.

The newly formed Data Sharing Eco Platform reportedly is the operational spine of Samsung’s push to run fully unmanned semiconductor fabs by the end of the decade, 2030.

Here’s what DSPE stands for

For years, Samsung kept that data locked inside its own walls. Security protocols made it nearly impossible to export error codes or processing times outside the factory.

DSEP opens a controlled slice of that process data to partners in real time, feeding it into AI models that can flag irregularities and predict failures without anyone boarding a flight.

This helps everyone (via SemiconductorsX):

• Find defects quicker
• Reduce bad chips (higher yield)
• Improve machines and materials using real factory info
• Use AI to predict problems before they happen

Samsung’s HPC Center inside its Device Solutions division already handles the infrastructure side. DSEP sits on top, connecting the partner ecosystem to that compute backbone.

Partners bring deep knowledge of their own equipment’s failure signatures. Samsung shares production-line data, partners sharpen their AI, and the whole system gets smarter.

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