China’s largest semiconductor manufacturer, SMIC, is currently hindered by its failure to acquire advanced EUV machinery to mass produce wafers on the 5nm lithography or below. With no alternative to scale past this limitation, the need for innovation and creativity is absolutely vital, so a new 3D IC stacking solution is rumored to be incorporated on Huawei’s upcoming Kirin 9050 to improve performance. The one positive to take away from the latest rumor is that the SoC can beat Apple’s older A18 Pro. New packaging technology will enable the Kirin 9050 to stack components vertically to increase transistor density and […]

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The U.S. sanctions may have closed Huawei’s trading capabilities with other countries to obtain access to the latest lithography and paraphernalia associated with mass producing next-generation chips, but what it also did was fuel the company’s desire to carve its mark without relying on overseas firms. Today, Huawei announced that by 2031, it will have chips with a manufacturing process equivalent to TSMC’s upcoming bleeding-edge 1.4nm process. While that sounds incredibly exciting, there are a few things we should keep an eye on. Achieving wafer manufacturing on a 1.4nm lithography isn’t possible without ASML’s High-NA EUV equipment, but Huawei may […]

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At the 2026 IEEE International Symposium on Circuits and Systems (ISCAS), Huawei’s He Tingbo showcased the company’s new “LogicFolding Design” technology during the “New Semiconductor Path in Practice” keynote. Hindered due to the lack of access to specialized EUV machinery, Huawei’s only path to remain a competitive entity against its chipset rivals is to innovate on the packaging side, with the advantages of this design including an impressive 53.5 percent increase in transistor design, along with a frequency boost of 12.7 percent. As for the other benefits, those have been detailed below. With further innovation, Huawei targets 2031 to reach […]

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