Fab 21 phase 2 shell is complete, fab is on track for equipment move in in mid-2026 and for volume production in 2027.

China has reportedly built and begun testing a secret EUV lithography prototype using ASML-style laser-produced plasma technology. Yet, despite generating 13.5-nm light, the system remains unable to make chips and appears to be years away from achieving a complete, production-ready EUV manufacturing capability.

Driven by demand for AI and HPC accelerators, sales of chip production equipment are projected to increase through 2027. Asian countries are expected to lead the pack, according to SEMI.

Rapidus plans to outline its early-stage work on panel-level packaging using 600 × 600 mm glass substrates at SEMICON Japan, highlighting an aggressive plan to leapfrog rivals by combining glass-core substrates and PLP for future AI and HPC chiplet packages.

Intel and imec demonstrate the first 300-mm, fab-compatible integration of contacts and gate stacks for 2D transistors, marking a critical step in turning long-studied 2D materials from lab experiments into a realistic future option for high-volume logic manufacturing.

Intel has installed and qualified ASML's TWINSCAN EXE:5200B, the first High-NA EUV lithography tool designed for commercial production, reiterating Intel's plans to use High-NA EUV patterning for 14A process technology and onwards.

Kioxia is reportedly pulling in mass production of high-capacity BiCS10 3D NAND devices with a 4.8 GT/s interface from 2027 to 2026, possibly to meet demand from AI, cloud, and enterprise storage sectors.

The rise of AI and hyperscale computing is driving a global shift from air-based to liquid and embedded cooling as various companies are developing silicon-integrated systems capable of handling multi-kilowatt system-in-packages that can be commercialized by 2027.

AWS's new 192-core Graviton5 processor with a massive 180 MB L3 cache marks the company's most ambitious in-house CPU yet, which could enable it to replace more AMD and Intel servers in its cloud.

JEDEC is nearing completion of SPHBM4, a standard that enables full HBM4 bandwidth over a 512-bit interface using a 4:1 serialization, reusing standard HBM DRAM dies and a base die. The tech promises to enable a 2.5D integration on organic substrates to support up to 64 GB per stack and more stacks than HBM4 and HBM4E.

Nvidia's GPU fleet management software can track spikes in power usage, monitor utilization, detect hotspots, spot anomalies, identify software errors, and detect the physical location of processors. However, the software is completely optional for its clients.