JEDEC has released its new specification that aims to push down the pricing of the ultra-expensive HBM that powers the fastest AI processors. While the new standard will not help relieve the DRAM shortage as it uses large HBM4 DRAM devices, it can make high-bandwidth memory a bit cheaper as it enables attaching SPHBM4 memory stacks without advanced packaging and using inexpensive organic substrates.

The standard's body published the specification of SPHBM4, Standard Package High Bandwidth Memory (JESD330-4), that combines HBM4 DRAM ICs with standard packaging and a fast 'narrow' 512-bit interface. Here are the details.

HBM4 performance with a 512-bit wide interface

Although 1024-bit and 2048-bit interfaces used by HBM3 and HBM4 memory deliver unbeatable performance, their wide interfaces consume significant silicon area inside processors, they require expensive interposers, and advanced packaging technologies with limited capacity, such as TSMC’s CoWoS, for integration with host processors. The upcoming SPHBM4 memory continues to use the same HBM4 DRAM stacks as JESD270-4, but swaps the conventional HBM base die for a new SPHBM4 PHY/buffer die featuring a narrower 512-bit interface that enables mounting on standard organic substrates without using sophisticated packaging methods for integration. To offset the effect of the narrower interface, SPHBM4 supports considerably higher data transfer rates ranging from 22.4 GT/s to 46.0 GT/s.

Instead of connecting to the host processor using a 2048-bit memory interface like HBM4, SPHBM4 uses 32 independent 16-bit DDR channels organized into eight Quad Channels. Since 'Quad Channel' is a new term, let us explain how things work. Internally, an HBM4 stack contains 32 memory channels, each 64 bits wide, for a total external interface width of 2048 bits. SPHBM4 needs to 'convert' the 2048-bit internal I/O onto a 512-bit external interface, which is why it groups every four HBM4 channels into a Quad Channel. As a result, externally, a Quad Channel exposes 64 data pins (4 × 16 bits), which replace the 256 data pins (4 × 64 bits) that those four HBM4 channels would normally require. To preserve bandwidth, these 64 pins operate at four times the data rate of the original HBM4 interface.

While SPHBM4 dramatically increases I/O bandwidth, it does not make the DRAM array itself faster. The HBM4 memory core retains the same fundamental architecture and timings, including core frequency, row activation, precharge, and refresh operations, though the additional PHY is expected to introduce some latency. For example, the DRAM core runs at only one-quarter of the external interface frequency, which means 2 GHz in the case of SPHBM4 with a 32 GT/s speed bin.

The major change is the new base die, which implements a high-speed SerDes-like PHY that maps each 16-bit external channel to four conventional 64-bit HBM4 channels. As a result, SPHBM4 introduces equalization, lane training, BER requirements, and other high-speed signaling features that are unnecessary in HBM4’s slower, wide parallel interface. To support transfer rates of up to 46.0 GT/s/s per pin, each Quad Channel uses a shared command/address interface protected by forward error correction (FEC), while data transfers rely on dedicated differential write (WCK) and read (RCK) clocks, as well as ECC and error-reporting signals.

When it comes to capacity, SPHBM4 can use stacks containing 4, 8, 12, or 16 DRAM dies featuring 24 Gb or 32 Gb densities, so the largest standardized SPHBM4 configuration is a 64 GB memory stack built from sixteen 32 Gb DRAM dies, identical to the maximum capacity supported by HBM4E.

Cheap HBM at last?

The standard supports bump pitches greater than 90 µm and channel reaches up to 20 mm, which are two features that enable dropping the expensive interposer and using less-expensive organic substrate routing. However, getting rid of the interposer and CoWoS (or similar) packaging does not automatically make SPHBM4 inexpensive. SPHBM4 still requires massive HBM4 DRAM ICs, 2.5D packaging, a complex base die (which is likely costlier than the one used by conventional HBM4), and advanced package assembly with through-silicon vias. In addition, SPHBM4's narrow interface consumes significantly less die perimeter and silicon area inside processors, which makes it more attractive to companies that strive to install more compute capability and/or intend to install more memory stacks around their processors. However, we are still talking about a niche high-performance memory technology that will address select applications and will barely rival HBM4 directly.

When it comes to maximum performance, HBM4 moves the data at 8 GT/s (though most controllers and chips support higher data rates), so one HBM4 stack can offer bandwidth of 2 TB/s. HBM4E is set to up data transfer rate to 12 – 12.8 GT/s, therefore increasing peak bandwidth to 3 – 3.3 TB/s per stack. By contrast, one SPHBM4 with a 46 GT/s interface can hit 2.944 TB/s, though do not expect the initial versions of SPHBM4 to hit the maximum speed. Therefore, it is likely that HBM4, HBM4E, and C-HBM4E will maintain a performance lead in terms of bandwidth over SPHBM4 in the foreseeable future.

HBM4 latency will still probably have an edge over SPHBM4. HBM4 essentially connects to its host processor almost directly through a very simple interface. By contrast, SPHBM4 inserts a much more sophisticated PHY that performs serialization/deserialization, lane training, FEC handling, and other operations that can add a few nanoseconds of latency. This may not be a big problem for some applications, but inference benefits a lot from low latencies.

When it comes to power and voltages, HBM4 and SPHBM4 share the same DRAM core voltage because SPHBM4 reuses standard HBM4 DRAM stacks. However, I/O is different: HBM4 leaves the interface voltage up to memory vendors and allows implementations at 0.7V, 0.75V, 0.8V, or 0.9V, depending on the desired balance between power, speed, and signal integrity. By contrast, SPHBM4 standardizes the external I/O at 0.75V.

Also, HBM4 moves data over a very wide interface with many slow parallel links that tend to be very energy efficient. By contrast, SPHBM4 moves the same amount of data through one-quarter as many wires, which run roughly four times faster. High-speed data transfer tends to be less energy efficient than 'slow' data transfers over a wide interface. Keeping in mind SPHBM4's rather sophisticated PHY that converts a wide interface into a narrow interface, which is likely a power-hungry process. Nonetheless, the 4X lower number of drivers and receivers could tangibly reduce the power consumption of SPHBM4. That said, without implementation details from DRAM makers or a processor developer, it is impossible to conclude which memory type has lower power consumption.

Last but not least, SPHBM4 essentially trades manufacturing challenges that arise from using silicon interposers for an engineering challenge of developing an extremely sophisticated base die/PHY. Developing and manufacturing such a base die should not be a problem for foundries. However, it remains to be seen whether DRAM makers can design and produce SPHBM4 with decent power efficiency. After all, both Micron and SK hynix work with TSMC to build C-HBM4E and HBM4E base dies, whereas Samsung's memory division uses base dies produced by Samsung Foundry.

China factor

One interesting aspect of SPHBM4 is whether Chinese developers of AI accelerators can benefit from this technology. In theory, Chinese developers like Biren, Huawei, Moore Threads, and other blacklisted companies that cannot use TSMC's chip manufacturing or packaging services could become one of the biggest beneficiaries of SPHBM4, perhaps even more so than the U.S.

First up, a smaller shoreline directly benefits chips that are made using trailing nodes, as it enables packing more compute capability into them without sacrificing memory bandwidth or capacity. Secondly, Chinese OSATs currently do not offer CoWoS-like technologies, so eliminating the interposer and using advanced organic substrates is a benefit.

However, SPHBM4 still requires HBM4 DRAM stacks, and today, Samsung, SK hynix, and Micron are the only companies capable of producing them, while China-based CXMT can barely make HBM2E. Furthermore, building a 46 GT/s PHY is very hard and will likely be challenging for Chinese IC developers.

Nonetheless, assembling SPHBM4 packages on organic substrates is arguably more aligned with China's existing manufacturing base, so if local DRAM makers eventually develop competitive HBM4-class memory, SPHBM4 could substantially reduce one of the country's remaining infrastructure gaps.

Summary

JEDEC's SPHBM4 looks like a promising standard that can potentially address a broader range of applications than HBM4 itself due to lower integration cost. Still, HBM4, HBM4E, and C-HBM4E will maintain performance leadership, which will make them a preferable choice for flagship AI accelerators in the coming years.

Sipearl has been developing a custom CPU, especially designed for high-performance workloads, named 'Rhea', for over five years. In late May, it was finally announced that the company had received the CPU from the fab, initiating the bring-up process, which is a significant milestone. The HPC CPU sports over 80 cores, in addition to an innovative memory subsystem. We spoke directly with Craig Prunty, vice president of marketing and business development of SiPearl, to learn the fine-grained details.

The Rhea CPU is intended to reach markets by late 2026 or early 2027, and won't be the most performant HPC CPU on the market. Regardless, SiPearl told us at Computex that there is interest both towards Rhea and its successors from rather unexpected parties, so the company is in with a chance to become a successful CPU designer over time.

Rhea's long road toward reality

SiPearl's Rhea (or Rhea1, how the company prefers to call the unit these days) sports 80 Arm Neoverse V1 cores with two 256-bit Scalable Vector Extension (SVE) engines for fast vector computations in FP64, FP32, BF16, and INT8 formats; 1 MB of L2 per core; 80 MB system-level cache (SLC), and 104 PCIe 5.0 lanes. The CPU has a unique memory subsystem comprising four HBM2E interfaces for 64 GB of on-package HBM2E stacks for applications that require massive memory bandwidth (think supercomputer applications like fluid dynamics) and four DDR5 interfaces supporting two 256 GB DIMMs per channel, for up to 2 TB of memory per socket. Rhea comprises 61 billion transistors and is fabbed by TSMC using its N6 process technology.

SiPearl received the first samples of its Rhea processor in mid-May, and the CPU is currently in bring-up mode. So far, it looks like the very first silicon works just fine, so the company will not have to respin it, which means SiPearl has a good chance of shipping it to customers in the coming quarters.

"The Rhea1 CPU is in its 12-week bring-up process since May 13, and it works exactly as it was designed to do," said Craig Prunty, vice president of marketing and business development of SiPearl, in an interview with Tom's Hardware Premium. "The test version of Rhea1 will be available for testing by partners and EU collaborative projects at the end of the bring-up process. The general availability of Rhea1 is scheduled for end of 2026."

Getting the very first silicon to work correctly is a stroke of good luck, especially for the very first product from a startup that has never designed a complex CPU before. However, it has taken the company over five years to define and then develop its processor, an unacceptably long cycle. With Rhea, SiPearl not only built its processor, but it actually built the company, Craig Prunty admitted in an interview with Tom's Hardware. The company once tried to work with a contract chip designer, but eventually canceled the deal and formed five in-house development teams in Europe. Since these teams have never worked together before, the processor was delayed a number of times from 2023 to 2026. It, of course, gained eight additional cores in the meantime, but this hardly justifies a three-year delay.

"We have five development teams in Europe: Maisons Laffitte, Massy (both in the Paris region), Grenoble and Sofia Antipolis in France, Barcelona in Spain," Prunty said. "The Bologna team is currently being put together."

One of the reasons why SiPearl has so many locations is that it wants to shrink its development cycle to around 18 months to offer competitive CPUs.

Now, because it is 2026, HBM2E memory is extremely hard to get, which is why Rhea1 will be a limited-run processor only available to select clients and partners. In theory, this is not something that is going to happen to SiPearl's Athena processor for aerospace, defense, and government applications, which is essentially Rhea with 16, 32, 48, 64, or 80 Neoverse V1 cores and without onboard HBM2E, which will be sold based on market demand sometime in 2028. Though, do not expect Athena to have a very long lifespan. SiPearl hopes to tape out its 2^nd Generation Rhea (Rhea2) processor in 2027. That CPU will not have onboard HBM, so its derivatives for aerospace, defense, and government systems will probably follow shortly, making Athena1 obsolete.

Opening unexpected doors

To a large degree, the first-generation Rhea processor is more than just a product for SiPearl, as it is meant to put the company on the map of data center and supercomputer CPUs and proof that a European entity can develop a competitive processor. SiPearl originally intended to address European supercomputers and sovereign AI infrastructure with Rhea1. However, many commercial cloud providers in Europe and the Middle East plan to evaluate the platform and even deploy it (albeit not widely) as they want to ensure they have access to technology in the current geopolitical situation.

While the CPU is the industry's third processor to use a hybrid memory subsystem comprising HBM2E and DDR5 (for which SiPearl deserves accolades), it is very late to market, so while it is natural that various sovereign AI and HPC deployments and Europe-funded supercomputers will deploy it, expecting commercial companies to deploy Neoverse V1-based machines in 2027 is pretty naïve. However, commercial companies will validate and test the platform, possibly do some software porting, and ensure that it works as intended. Some companies might even deploy Rhea1 in their data centers. As Craig Punty puts it, Rhea1 could open rather unexpected doors for SiPearl.

As it turns out, geopolitical tensions and export controls force big players to look for alternatives to American hardware, which is where SiPearl's processors could fit rather well. SiPearl is based in France, it has R&D centers around Europe, it licenses technologies from Arm, and produces its CPUs in Taiwan. The company cannot ship its CPUs to China due to export restrictions, but it can sell them to clients in Europe and the Middle East without restraint, which is its indisputable trump card. Assuming that SiPearl offers competitive performance, its CPUs are almost guaranteed to be adopted by sovereign AI and HPC deployments in Europe, which means guaranteed revenue.

One might argue that since SiPearl uses Arm's cores, it will inevitably compete against Arm's AGI processors eventually. Indeed, it will, once its CPUs address large CSPs. Which is why the company must stay ahead of Arm's own offerings in terms of performance and features, or at least be on par with them.

Seine reference server

For now, SiPearl is bringing up its Rhea1 processor in its labs. The company already has its Seine reference server design that is primarily designed for validation, testing, evaluation, and software porting. For AI and HPC deployments, Seine can be configured for one Rhea CPU and two accelerators; for more traditional supercomputer needs, two Seine motherboard can be installed into one chassis, though the nodes will work independently.

Speaking of the Seine motherboard, it should be noted that since SiPearl uses it for bringing up the CPU, it had to be made perfect so to exclude any possible problems on its side. To that end, it uses costly components and an ultra-expensive 26-layer printed circuit board to ensure signal integrity, reduce crosstalk, provide the best quality power possible, and ensure maximum mechanical stability.

The Seine server reference design will be used by Bull to build servers for the Jupiter supercomputer, according to Prunty. Other server suppliers may follow and adopt the same design to offer their servers based on Rhea1.

"We had also a partnership agreement signed with HPE to work together on European supercomputers tender offers," Prunty said. "Our CPUs will also equip other servers as part of European AI gigafactory project."

Sipearl's Rhea readies up

Developing a supercomputer-grade processor in Europe is already quite an achievement, but developing a CPU that works fine from the first silicon could indeed be considered a breakthrough for a startup. In addition, SiPearl tapes out its Rhea in a good time when potential customers may adopt it despite the fact that Neoverse V1 technology that powers the chip is outdated. As it turns out, export controls made not only sovereign AI and HPC deployments look in SiPearl's direction, but private CSPs in Europe and the Middle East also plan to evaluate its processors.

SiPearl admits that a five-year development cycle is too long for a modern CPU, though it remains to be seen whether it can indeed shrink it to 18 months. The company already has five development sites and is building another one, so it looks like it the company is on the right path. Yet, SiPearl must prove that it can develop Arm-based processors that are competitive against Arm's own AGI as well as other Arm-powered data center CPUs, something that will not be easy to do given the fact that SiPearl is a startup, whereas its potential rivals are billion-dollar companies.

Of course, SiPearl will always have a couple of trumps up its sleeve: the European Processor Initiative (EPI) as well as sovereign AI and HPC deployments that will always prefer locally developed CPUs no matter what. Whether such businesses are enough to build a world-class processor developer is something that remains to be seen, but at the very least, SiPearl will not vanish into oblivion like many other European CPUs makers.

Kioxia and Sandisk last week said they had started sampling of their latest 3D NAND memory with 332 active layers that features a combination of the industry's leading areal density and performance. The new 10th Generation BiCS 3D TLC NAND is set to address density and performance-sensitive data center applications, as well as promises to surpass Samsung’s latest V10-class 3D NAND in terms of storage density.

Unlike the previous generations, 10th Generation BiCS (BiCS10) is explicitly aimed at data center-grade storage, where bit density and performance are more important than cost. Indeed, the new type of memory features a 332-layer active layer architecture, greater than 29 Gb/mm² density, and a 4,800 MT/s data transfer rate to enable extreme performance for data center solid-state drives featuring PCIe 5.0 and 6.0 interfaces. Kioxia and Sandisk plan to offer BiCS9 NAND specifically for client applications.

When we normally describe 3D NAND memory, we usually mention all possible applications, which include high-end consumer SSDs (after all, we are Tom's Hardware, we are hardware enthusiasts!) and data center drives. We did not mention consumer applications for BiCS10 for a very specific reason: Kioxia does not position this generation for client devices and only targets data center-grade drives. Whether or not to expect BiCS10 on a high-performance SSD near you probably depends on supply and demand, given the current market circumstances.

While the BiCS10 332-layer 3D NAND boosts bit density by 59% all the way to over 29 Gb/mm², it also promises to deliver meaningful performance and efficiency gains specifically for enterprise applications. Kioxia claims read latency drops by around 4 microseconds (about 10%), while read energy consumption is reduced by 25%, from roughly 100 mJ/GB to approximately 75 mJ/GB.

According to Kioxia, these improvements stem from a redesigned read scheme that changes how unselected word lines behave during consecutive read operations. In a 332-layer NAND stack, a significant portion of read latency and power consumption is associated with repeatedly charging long word lines from ground (VSS) to the read voltage (VREAD).

Normally, NAND memory discharges its wordlines to ground (VSS) after every read, which is a general-purpose approach that works regardless of what the next operation is. However, there is no need to discharge at all times. Therefore, during continuous read operations, the word lines are not fully discharged in the case of BiCS10. Instead, they are lowered to an intermediate voltage and then raised back to VREAD for the next read, which makes a lot of sense for read-heavy applications (most cloud applications are).

After the initial read, the circuitry reduces the word-line voltage only to an intermediate level instead of completely discharging it to VSS. Before the next access, the voltage is restored to VREAD from that intermediate level rather than from ground. Since the voltage excursion is considerably smaller, the word lines recharge more quickly and require less current, which improves both read latency and energy efficiency. The approach is particularly beneficial for very tall 3D NAND stacks, where long word lines amplify charging delays and power losses during sustained sequential read workloads.

It is interesting to note that Kioxia and Sandisk plan to manufacture their BiCS9 and BiCS10 3D NAND products at different production sites. The newest Fab 2 facility in Kitakami, Iwate Prefecture, will handle production of the flagship 332-layer BiCS10 memory, while the long-established Yokkaichi complex in Mie Prefecture will continue manufacturing the 218-layer BiCS9 generation.

This manufacturing split makes a lot of sense. Fab 2 is equipped with Kioxia’s most advanced production tools, so it is better suited to manufacture the highest-density NAND from Kioxia and Sandisk. Meanwhile, the mature Yokkaichi fabs are well-suited for client-oriented BiCS9 production. The manufacturing facility has largely been depreciated, which enables the company to manufacture mainstream NAND at lower cost and reserve its newest capacity in Kitakami for leading-edge products.

Intel on Friday confirmed that it had increased prices of some of its consumer and server CPUs, citing market dynamics, rising costs, and soaring demand for these products. While select enthusiast processors increased from $30 to $50, data center-grade products increased by hundreds, if not thousands, of dollars. Intel is among many suppliers that have recently hiked prices of their products, citing increasing costs and demand that exceeds their supply.

"The recent pricing updates reflect current market dynamics, including rising supply chain costs and strong demand for our Intel Core Ultra 200S Plus processors," an Intel spokesperson told Tom's Hardware. "These updates are in line with recent price increases for other Intel product families based on similar factors."

This week it turned out that Intel had quietly increased recommended customer prices (RCPs) of its latest Core Ultra 200-series Plus processors for desktops — the Core Ultra 7 270K Plus and the Core Ultra 7 250K Plus — by $30 - $50, depending on the model. Both processors belong to the Arrow Lake family and, like the rest of them, are produced by TSMC. Yet, Intel's original 'non-Plus' Core Ultra 200-series processors did not increase their MSRP. The flagship Core Ultra 9 285K still carries a $599 RCP, just like it did at its launch in Q2 2024. Something similar applies to the least advanced Arrow Lake processor for desktops — the Core Ultra 5 225 — that has an RCP between $183 and $236, which is a bit lower than its launch RCP of $241.

If Intel did see supply-chain inflation, it would be reasonable to expect the company to adjust prices of the whole family. Instead, the company raised prices only on select products that apparently had become unexpectedly attractive to customers who can afford them and who have probably demonstrated willingness to buy them above recommended prices. This means that we are not dealing with a simple cost pass-through, but rather with a price hike associated with strong demand for specific SKUs.

When it comes to data center-oriented processors, we see rather massive price hikes. While higher-end Xeon 6 'Granite Rapids' CPUs cost less than they used to at launch in 2024, they are noticeably more expensive after Intel slashed their recommended prices in 2025, and they can be twofold higher when compared to retail prices from mid-2025. Perhaps the biggest surprise is that select Xeon 8000-series 'Emerald Rapids' processors now carry higher RCPs than they used to when they were released in late 2023.

All Intel Xeon processors are produced internally (so Intel cannot blame higher costs on TSMC), and while Intel gets raw materials from its partners, it is doubtful that overpriced photoresist can significantly affect RCPs of CPUs that sell for thousands of dollars. Meanwhile, Intel has been saying for several quarters now that demand for its Xeon processors exceeds supply. Therefore, it makes a lot of sense for Intel to finally capitalize on that and increase RCPs of popular models.

There is a caveat, though. Actual prices of data center hardware tend to differ from list prices as they depend on many factors, including volumes and strategic relations between suppliers and consumers. To that end, while it is evident that Intel has increased RCPs of its Xeon CPUs, it remains to be seen how this affects its average selling prices (ASPs) for the ongoing quarter and for the whole year.

Intel has resolved wafer-to-wafer yield variability issues with its 18A process technology, according to a report from BlueFin Research Partners. If the report coming from an unofficial source is accurate, then Intel can expect consistent and predictable yield improvements for its products made using the latest 1.8nm-class node from now on.

"Intel 18A wafer-to-wafer yield issue resolved; ramp to 12-15K wpm at both sites ongoing," BlueFin Research Partners wrote in a note to clients.

If the information is accurate, then products made using Intel's 18A process technology will no longer be plagued by wafer-to-wafer variability, an issue where good wafers and poor wafers are produced in the same production flow. However, wafer-to-wafer variability is only one contributor to yield loss, so fixing it means that Intel can now consistently improve product yields, but it does not necessarily mean overall yield is where Intel wants it to be.

Generally, a die yield defined by multiple factors, including defect density (which in turn is defined by random defects and systematic defects), within-wafer variability (differences between the center and edge of the same wafer when it comes to things like critical dimensions uniformity, line edge roughness, or stochastics; something that Intel has been improving recently), wafer-to-wafer variability (die yield and/or parametric yield differ from wafer to wafer), and packaging yield. When it comes to actual products, we should mention parametric yields (dies may be defect-free, but they do not meet performance and/or power specifications) as well as reliability screening (dies are functional and meet required specifications but fail burn-in tests).

That said, saying that Intel has 'fixed wafer-to-wafer yield issues' most likely means the process is now much more consistent from wafer to wafer, which clearly reduces lot-to-lot variation and makes production more predictable. However, it does not mean that defect density has reached target levels, parametric yield is optimal, and overall economic yield is where Intel wants it to be. What it does mean is that at a consistent yield improvement level (Intel once mentioned 7% per month for 18A), Intel is set to reach its target goals within a predictable timeframe.

In addition, the report claims that Intel now has capacity of around 30,000 wafer starts per month across its D1X development fab (presumably module 3) in Oregon and Fab 52 high-volume fab in Arizona (confirmed by @Alex_Intel_), which is a solid result at this point of the ramp cycle. However, without information about overall die yields and parametric yields of Intel's 18A products, it is hard to assess whether Intel can now produce enough Core Ultra 3 'Panther Lake' and Xeon 6+ 'Clearwater Forest' processors. Meanwhile, it should be noted that using a development facility for high-volume manufacturing (HVM) is costlier than using a fab that was designed to be an HVM fab from the start.

Meanwhile, it looks like Intel is set to continue such a practice with its next-generation 14A (1.4nm) fabrication process, according to BlueFin. The company plans to make 'D1X the initial HVM fab for 14A,' whereas the first phase of Intel's Ohio One semiconductor manufacturing site in Ohio will serve as the second HVM facility to make 14A chips, BlueFin claims. Intel recently confirmed that it intends to initiate high-volume production of chips using 14A in 2029. Ohio One first phase (Mod 1) is set to be completed in 2030, which means that it will come online 'between 2030 and 2031,' according to Intel.

SK hynix this week announced that it would invest an additional KRW 100 trillion ($64 billion) in its Cheongju campus to expand production of 3D NAND and HBM packaging at the site. Given the vast investment, expect the company to add some massive production capacity, but unfortunately that production capacity is going to kick in only several years down the road. But that investment pales in front of the company's plan to invest $712.5 billion in its South Korean operations.

The massive KRW 100 trillion ($64 billion) in its Cheongju campus investment is only a part of SK hynix's grand plan to invest KRW 1.1 trillion ($712.5 billion) in a variety of projects in South Korea. In particular, the company intends to invest KRW 400 trillion ($259.5 billion) in its all-new Southwestern semiconductor cluster as well as KRW 600 trillion ($389.3 billion) in its Yongin site. While the Cheongju investment is considerably lower than investments in other campuses, it is the only project that is actually detailed enough.

$64 billion go to Cheongju to support NAND and packaging

SK hynix claims that it intends to build a 3D NAND fab, install manufacturing equipment, and expand its advanced packaging capabilities for HBM back-end processing at its Cheongju campus in the Chungcheong region. The company intends to start building its M17 fab next year, so the earliest timeframe it comes online is sometimes in 2029 at the earliest. The fab will cost around KRW 80 trillion ($51.8 billion), whereas the new P&T7 packaging and test facility will cost KRW 20 trillion ($12.945 billion).

SK hynix's campus in Cheongju houses some of the company's primary fabs that manufacture 3D NAND flash, including M11, M12, and M15, and historically it was the company's main 3D NAND memory manufacturing center. However, because multi-layer 3D NAND and high-bandwidth memory (HBM) stacks use similar packaging technologies, it is now evolving into a site that also makes HBM stacks: M15X produces actual DRAM dies, whereas P&T3 performs packaging operations.

But the investment in SK hynix's Cheongju NAND and HBM assembly operations pales when compared to how much money the company plans to pour into other projects.

$389.3 billion go to Yongin Semiconductor Cluster to boost DRAM output

SK hynix plans to invest approximately $389.3 billion in the Yongin Semiconductor Cluster, which is the company's largest investment commitment ever and which will make the campus its largest DRAM production site. Meanwhile, Yongin is a greenfield site today.

The first fab in Yongin is expected to commence operations in May 2027, while the remaining fabs will be added sequentially. It takes about a year or 1.5 years or so to fully ramp a DRAM fab, so expect the facility to impact the memory market in 2028 – 2029. Under the company's newly announced plan, construction of all four fabs is now targeted to complete the fourth fab by 2033, instead of the original 2045 timeline. The $389.3 billion investment extends beyond 2033.

$259.5 billion go to Southwestern Semiconductor Cluster

Unlike Yongin, the Southwestern Semiconductor Cluster does not even exist. It is currently a planned project, and SK hynix has not even selected a specific site within southwestern Korea. The company says the exact location will be determined after evaluating land availability, electricity, water, transportation, and other infrastructure requirements in consultation with central and local governments.

The cluster is envisioned as SK hynix's next major manufacturing base after Icheon, Cheongju, and Yongin. For now, the planned investment totals approximately $259.5 billion, though given that the project's completion is decades away, we can expect that number to change upwards or downwards depending on the market conditions and the cost of wafer fabrication equipment.

The investment will be phased over many years and cover land acquisition, fab construction, and production tools. SK hynix says preparations must begin now because developing a new semiconductor cluster — including site selection and infrastructure — takes many years. For example, development of the Yongin Cluster took about nine years, according to SK hynix.

Not alone

SK hynix is not alone in investing in South Korea. Samsung on Thursday announced plans to spend some KRW 140 trillion ($90.98 billion) in its operations in South Korea’s Chungcheong region.

Under the plan, Samsung Display will expand OLED production in Asan; Samsung Electronics will build five HBM production lines in Onyang and modernize HBM-related facilities in Cheonan; Samsung SDI will establish a battery production line in Cheonan to validate next-generation technologies before deploying them globally; and Samsung Electro-Mechanics will expand AI server package substrate manufacturing in Sejong.

Intel this week initiated expansion of its Bowers Campus in Santa Clara, California, in a bid to produce more photomasks (reticles) in the U.S. The company intends to build a new manufacturing facility and a new utility building at the site, which will reinforce the site's position as a key producer of photomasks for Intel.

Earlier this year Intel obtained approval to build a new 107,000 square feet (9,940 square meters) manufacturing facility with Class 1 cleanroom at its Bowers Campus, and this week it formally began construction on the expansion, which it kicked off at a ceremony attended by its top executives and Santa Clara mayor Lisa Gilmor. The new facility will be able to write 6-inch × 6-inch photomasks both for DUV and EUV layers and a variety of nodes (from 32nm down 1.4nm-class), though the primary focus of the facility is to produce reticles for leading-edge process technologies — such as Intel's 18A, 18A-P, 14A, and more advanced — that rely on advanced DUV, EUV and eventually High-NA EUV tools and require more advanced photomasks, such as those that feature extremely dense patterns and use curvilinear optical proximity correction (OPC) with curved geometric shape.

Intel is one of a few leading chipmakers in the world that still maintains a world-class mask writing shop — which is important, as every advanced product requires hundreds of masks, and every mask revision directly affects production schedules. In addition, producing masks in-house is getting particularly important when it comes to reticles for EUV layers as EUV tools tend to damage masks over time (despite usage of protective pellicles), so having the ability to make new masks in a short amount of time is crucial.

Furthermore, Intel is the only semiconductor producer to make its own tools for photomasks writing at its IMS Nanofabrication subsidiary. Historically, reticles were patterned using a single e-beam tool, which was slow. By contrast, IMS produces multi-beam mask writers (MBMWs) that project 262,144 independently programmable electron beams simultaneously, which increases throughput by orders of magnitude at a nanometer-scale placement accuracy.

"Santa Clara has been home to some of Intel's most important manufacturing innovations for decades," said Dr. Frank Abboud, VP Intel Foundry & GM of Intel Mask Operations. "By expanding the Bowers campus mask operations, we're strengthening a critical capability that supports advanced process technology production around the world and reinforces Intel Foundry's commitment to advancing U.S. semiconductor manufacturing leadership."

Intel's Bowers Campus in Santa Clara has been dedicated to mask production since 1986. The site forms the company's primary mask manufacturing infrastructure supporting together with the company's facility in Hillsboro, Oregon. Production of non-critical masks has historically been outsourced, though we do not know whether the company still does that.