Jensen Huang, chief executive of Nvidia, denied reports about delays of the company's next-generation AI platform and said that production volumes of the upcoming Vera Rubin platforms are 'giant.' He didn't address reports about delays of Vera Rubin Ultra-based rack-scale systems carrying 144 AI GPUs.

"[The reports about Vera Rubin delays are] not true," Huang told reporters on the sidelines of an event in Japan, reports Bloomberg. "Vera Rubin is already in production. Giant amounts of production incoming."

Nvidia confirmed production of its Vera Rubin platform in January and then sampling in February, so the current comment reiterates what we already know. Nvidia stressing that 'giant amounts of production' are incoming is meant to reassure investors that the company is on track to sell a boatload of its next-generation Vera CPUs, Rubin GPUs, and Vera Rubin NVL72 systems in the coming quarters, which means more record-setting quarters.

What Huang did not address — or perhaps he wasn't asked — is Nvidia's rumored delay of its Kyber NVL144 rack-scale solution with copper interconnects due to the system's complex PCB midplane by more than a year from 2027 to 2028. An alternative dual-rack design has reportedly been canceled and an even larger CPO-based NVL576 configuration may also face delays or limited availability, the same report from SemiAnalysis claimed earlier this month. The setback could leave Nvidia's Rubin Ultra platform with a smaller NVLink scale-up domain than originally envisioned. Nvidia says its roadmap is intact.

The Kyber NVL144 architecture was designed to connect 144 Rubin Ultra GPUs using a copper-based NVLink 7 scale-up fabric, so the machine required a sophisticated PCB midplane to carry high-speed electrical links between the system's components. SemiAnalysis claims that this midplane was challenging to manufacture, leading to a delay. The report does not identify defective chips or problems with particular components mounted on the board, but specifically points to the manufacturability of the PCB infrastructure itself.

"Our roadmap is intact," a spokesperson for Nvidia told Tom's Hardware.

Nvidia's statement on the matter neither confirms nor denies the report, but indicates that the company will be able to offer products mentioned in its roadmap without revealing whether they also remain on their previously announced launch schedules.

Nvidia reportedly considered another copper-based design, called NVL72x2, as an alternative to Kyber. The system would have placed two Oberon racks back-to-back to expand the size of the NVLink scale-up domain without using optical interconnects. However, SemiAnalysis says customers rejected the unusual design and operational requirements, but does not specify their individual objections that could include serviceability, cooling, cabling, and data-center layout.

Meanwhile, the planned NVL576 rack scale solution that was supposed to combine eight Oberon racks interconnected using co-packaged optics between NVSwitches has also been postponed, or shipped in relatively small quantities because of 'ongoing CPO challenges,' SemiAnalysis claims.

The existence of the planned NVL576 configuration suggests that Nvidia had been developing some form of CPO-enabled NVSwitch connectivity for the Rubin generation. In theory, similar optical switch-to-switch connectivity could potentially be used to join smaller GPU groups into an NVL144 system and bypass Kyber's problematic copper midplane. However, the available information does not clearly indicate whether the CPO technology intended for NVL576 could reproduce Kyber's topology, bandwidth, and latency characteristics, or whether it was sufficiently mature for high-volume deployments by potential NVL144 customers.

The reported Kyber delay comes on the heels of another report saying that Nvidia had canceled quad-compute-chiplet version of its Rubin Ultra in favor or a dual-compute-chiplet design that is projected to deliver 2X lower performance. With Kyber NVL144 delayed and NVL72x2 cancelled, Nvidia will only be able to offer 72-way scale-up systems till sometimes in 2028, meaning that AMD and Google may end up with more competitive scale-up systems in 2027 – 2028. AMD's Mega Pod based on the Verano CPUs and Instinct MI500-series accelerators, is expected to pack up to 256 accelerators. Google's TPU 8i can provide roughly 1,024–1,152 accelerators within one low-latency domain, whereas the TPU 8t goes much further and can get to 9,600 chip packages per domain.

Google plans to use Intel's EMIB-T packaging for its next-generation TPU codenamed Humufish, according to SemiAnalysis. TSMC's portfolio of chip-on-wafer-on-substrate (CoWoS) technologies has become the de facto standard advanced packaging option for nearly all AI and HPC processors made in the industry. Competing offerings are usually considered as secondary solutions if CoWoS is in tight supply, but things are beginning to change.

Google is a long-standing CoWoS customer for TPUs, starting from the Third-Generation TPU, all the way to Google's latest Eighth-Generation TPUs. Assuming that SemiAnalysis's report about Google's decision to move to EMIB-T with its Ninth-Generation TPUs is accurate, it's a big decision for Google, as switching from one advanced packaging technology to another is a complicated endeavor, which involves plenty of changes and unknowns. Understanding Google's reasons for the switch could shed some light on the prospects of Intel's and TSMC's advanced packaging technologies, which will be used by leading chip designers and hyperscalers in the coming years.

Advanced packaging technologies at glance

For years, Google used TSMC's CoWoS-S, and later, CoWoS-L packaging. Initially, the company used CoWoS-S packaging, which relies on a silicon interposer up to 3.3X the reticle size, but with its 7th- and 8th-Generation TPUs, the company moved to CoWoS-L. CoWoS-L relies on a redistribution layer (RDL) interposer with embedded local silicon interconnect (LSI) bridges that enable high-performance die-to-die links, which can scale packages to 5.5X the reticle size today. TSMC promises to improve CoWoS-L's capabilities to scale over 14X the reticle size by the end of the decade.

Unlike CoWoS, Intel's embedded multi-die interconnect bridge (EMIB) technology does not use any interposers. The technology instead relies on tiny embedded silicon bridges within the substrate to enable high-density die-to-die interconnections, whereas everything else is routed through an inexpensive organic substrate.

EMIB-T adds through-silicon vias (TSVs) to the bridge, which enables power to flow vertically instead of going through the organic substrate. In addition, Intel's EMIB-T also integrates sophisticated metal-insulator-metal (MIM) capacitors and a dedicated ground plane into the bridge to improve power integrity. The latter is a particularly important feature of complex next-generation AI accelerators, which demand more, cleaner power, and for which power delivery is becoming as challenging as signal routing.

The main selling point of EMIB (and EMIB-T) is that it is not constrained by interposer reticle limits as it places small silicon bridges only where high-density die-to-die links are needed. Strictly speaking, CoWoS-L is not either, as it uses LSIs locally as well. The difference is that those bridges are embedded into a package-wide RDL interposer that connects everything and enables dense interconnections across the package.

Since both CoWoS-L and EMIB-T are designed to address the same applications and have many similarities in the way they do this, the choice between them is likely driven by a combination of factors rather than one single advantage or disadvantage. On the technology side of matters, these factors include interconnect performance and density, power delivery, scaling beyond very large package sizes, and mechanical rigidity. On the business side of things, costs, capacity availability, and supply chain diversification are also a significant factor.

Crucial differences

SemiAnalysis claims that the main advantage of EMIB/EMIB-T over CoWoS is the lack of reticle limit, but this argument does not fully hold against CoWoS-L, as it was invented specifically to escape the reticle limitation by replacing the monolithic silicon interposer with localized LSI bridges.

When it comes to dense, package-wide routing, CoWoS-L's RDL interposer is fundamentally superior to an ordinary organic substrate offered by EMIB-T. Organic substrate wiring has coarser line/space dimensions and larger vias, so it cannot provide the same routing density as CoWoS-L's fine-pitch RDL. Where an EMIB bridge connects adjacent dies, Intel can achieve very high interconnect density. But anything that needs to travel beyond those bridges must use the package substrate or cross a topology involving additional bridges.

By contrast, CoWoS-L gives the designer two levels of connectivity: LSIs provide extremely dense local die-to-die connections, while the global RDL interposer provides relatively dense and flexible routing across the entire package. This means the RDL can carry longer, lower-density connections without consuming valuable LSI resources, while still offering much finer routing than the underlying package substrate.

One scenario for Google's choice is that it potentially wanted better power delivery than what CoWoS-L could offer. EMIB-T integrates TSVs for vertical power delivery, sophisticated MIM capacitors for local decoupling, and a dedicated ground plane into its silicon bridges. The combination of these features substantially reduces power-delivery impedance and improves transient response and power integrity, which gives EMIB-T a major advantage over conventional EMIB for power-hungry AI accelerators. However, we have no idea how EMIB-T stacks up against CoWoS-L in the case of Google’s Humufish.

Of course, the larger the RDL interposer becomes, the greater its parasitics can become, potentially limiting scaling unless TSMC finds ways to mitigate them. However, EMIB does not eliminate long-distance wiring: If two distant dies must communicate, those signals still have to travel somewhere, and routing them through an organic substrate is not inherently electrically superior to routing them through a purpose-built RDL interposer. Therefore, it is difficult to claim that Google chose EMIB-T over CoWoS-L, simply because EMIB-T offers superior package-wide electrical characteristics.

After Nvidia suffered yield loss with its Blackwell data center GPUs due to an alleged mismatch in the coefficient of thermal expansion (CTE) among the GPU chiplets, LSI bridges, RDL interposer, and motherboard substrate, which led to warping and system failure, it is reasonable to question the mechanical rigidity of CoWoS-L packages. Nvidia has found a solution for its dual compute chiplet Blackwell packages, and so have other developers of AI accelerators. However, as package dimensions increase, they may behave differently, therefore causing yield losses.

By contrast, EMIB/EMIB-T eliminates the large RDL interposer and embeds small silicon bridges in the organic substrate, so most of the package consists of the substrate itself. This does not make EMIB/EMIB-T packages immune to mechanical failures, as large packages can warp and bend, causing various problems. However, as such packages lack the very source of global thermomechanical stress, they can potentially be more robust mechanically. However, EMIB-T can potentially complicate things because TSVs, additional metal structures, MIM capacitors, and their ground plane make the bridge more complex. Thus, Intel must manage both global package warpage and local stresses around each embedded bridge to ensure the mechanical rigidity of these packages.

Ironically, while CoWoS-L can offer denser package-wide routing, which is better for ultra-large processors, EMIB-T may potentially provide better mechanical rigidity required for such devices. Nonetheless, EMIB-T and its organic substrate do not eliminate package bending or cracking risks entirely.

Economics

If Google's Humufish TPU really moves to EMIB-T, the decision could well be both technical and strategic. Google has the engineering resources to opt for an all-new packaging technology in an effort to lower costs and eliminate dependence on TSMC's constrained CoWoS capacity. Nvidia tends to procure advanced packaging allocations years in advance, so it is possible that Google could simply not get enough CoWoS-L wafers for its 9th-generation TPU.

As a bonus, Google can also build relationships with Intel Foundry without using the company's fabrication technologies. In fact, keeping in mind that Intel and Google already have a strategic agreement covering Intel Xeon CPUs, it wouldn't be too surprising to learn that the cloud giant is courting Intel Foundry as well.

Both Intel's EMIB-T and TSMC's CoWoS-L have their own technological and economic advantages and disadvantages. Perhaps the biggest advantage of CoWoS-L is its predictability, as the company has experience with that tech. However, if Google has decided to drop that predictability in favor of an all-new packaging method, it may well have a combination of technological and strategic reasons to do so.

Nowadays, storage devices for consumer and data center applications differ rather dramatically, as do approaches to product design as well as go-to-market strategies. Therefore, to get a more or less comprehensive overview of the storage market in general, you must observe both ends of the spectrum. To complement our interview with Nelson Duann at Computex, we also sat down with his colleague Alex Chou, who is in charge of Silicon Motion’s enterprise storage business.

Alex Chou is an interesting person to talk to. Before joining Silicon Motion, he spent some 18 years at Broadcom, where he led the wireless connectivity business, also initiating the Enterprise Switch, PoE, and 10-G Base-T PHY business with a product marketing focus. Before that, he worked at UMC Capital, ARK Logic, and Western Digital, where he developed graphics accelerators. He deeply understands the industry and uses his knowledge to expand SMI's business into the data center segment. As he is the first general manager of Silicon Motion's enterprise business unit, it is safe to say that all the success that the company has faced in the new segment so far can be attributed to Alex Chou.

Anton Shilov: Can you introduce yourself to our readers, please?

Alex Chou: My name is Alex Chou. As you know, Silicon Motion has two business units: the client business and the enterprise business. I am responsible for the enterprise business unit. My responsibilities include defining new products, leading development teams, bringing products to market, and working with OEMs, cloud service providers, and other customers to promote our technology and differentiation.

Getting into enterprise SSD business

Historically, Silicon Motion was focused on NAND controllers for client applications as well as embedded graphics processors and USB display controllers. Following the restructuring in the early 2020s, SMI formed a separate business unit to offer enterprise-grade SSD controllers, though it took the company some time to land its first tangible orders. By now, the company has yet to grab a 10% market share, yet it has clients among cloud service providers (CSPs), hyperscalers, and OEMs, significant achievements given Silicon Motion is a relatively new market entrant.

Anton Shilov: It has been a challenging year for much of the industry, particularly for memory-related segments. Yet Silicon Motion reported first-quarter revenue of $342.1 million, up 23% sequentially and 105% year-over-year, while SSD controller sales increased by roughly 40% to 45%. Can you explain what drove those results, particularly on the enterprise side?

Alex Chou: It depends on how you define a difficult year. If you look at the results, I would argue that this has actually been one of the best years the storage industry has seen.

Silicon Motion is fundamentally a controller company. We build controllers that work with NAND from all major memory suppliers. On the enterprise side, we are still relatively new compared to some established competitors, but we have secured a number of new projects and have started delivering products to customers.

We have invested heavily in PCIe Gen5, Gen6, and Gen7 enterprise SSD controllers. Today, our Gen5 products are beginning to ramp into volume production with multiple OEM customers. That ramp is contributing to our growth.

Anton Shilov: Do you have an estimate of your market share in the enterprise SSD controller market?

Alex Chou: That depends on how you define the market. Some people measure market share by unit shipments, while others look at exabytes shipped because SSD capacities continue to increase.

We have only recently begun shipping enterprise products in volume. If you listened to our CEO's comments during the earnings call, we expect enterprise shipments to increase significantly in the second half of the year. We are still in the early stages of our ramp, but we are making good progress with several key customers.

If you look beyond the initial ramp and think about the full-year run rate, I believe we can build from there and target a much stronger position next year. Longer term, our goal is to exceed 10% market share in the $4B enterprise SSD controller market, but this year is really about getting through qualification, customer testing, and the early production ramp in 2 half of this year.

Our goal is to continue expanding our share. We are only beginning the ramp [of our data center-grade SSD controllers] today, but we expect our share to increase meaningfully as deployments grow.

Anton Shilov: Who are your primary customers? SSD manufacturers, OEMs, or hyperscalers?

Alex Chou: We primarily work with OEMs. We sell controllers and firmware solutions to SSD manufacturers and OEMs. Some customers use our complete controller-and-firmware solution, while others develop their own firmware.

At the same time, we work directly with hyperscalers and cloud service providers to explain the advantages of our products and ensure they understand our technology roadmap.

Enterprise SSDs are used in several different segments. Traditional compute servers represent one market. High-density storage systems used for AI and large-scale data storage are another. We also see growing interest in storage systems located near GPUs, where latency becomes particularly important.

One area where we differentiate ourselves is quality of service. We have developed a patented traffic-shaping engine that helps maintain latency consistency under heavy workloads and multi-tenant environments. That capability is particularly attractive to hyperscalers and cloud service providers.

Anton Shilov: Do you see the enterprise SSD market splitting into different categories depending on workload?

Alex Chou: Yes. We see at least three major categories emerging.

The first is traditional compute-attached enterprise SSDs, which are used in conventional servers and storage systems. The second is very high-density storage for AI and hyperscale environments, where capacity, throughput, and cost efficiency are critical. The third is storage located closer to GPUs, where the requirements are very different because latency and quality of service become much more important.

That third category is particularly interesting. In AI systems, the storage subsystem is no longer just feeding CPUs. It increasingly has to support GPUs directly, especially for workloads involving very large datasets or KV-cache offload. In those environments, low latency and predictable performance matter much more than they did in traditional storage deployments.

Storage Next, PCIe 6 and PCIe 7 SSD controllers

Anton Shilov: Is that where Nvidia's Storage Next vision comes in?

Alex Chou: Yes. Storage Next is one of the major industry developments we are watching very closely.

The idea is that storage will move closer to the GPU and become part of a much more tightly integrated data path. In some cases, the goal is not just to maximize bandwidth, but to ensure that latency remains low and deterministic enough for AI workloads that continuously move data between accelerators, system memory, and storage.

This is one of the reasons we have invested heavily in QoS and latency control. Through our traffic-shaping technology, we can manage access patterns and reduce latency spikes when multiple tenants or applications share the same SSD. In a cloud environment or an AI storage environment, that becomes very important.

Anton Shilov: So, the challenge is no longer just raw throughput, but how predictably the SSD behaves under load?

Alex Chou: Exactly. Bandwidth still matters, but in many enterprise and AI environments, consistency matters just as much.

When multiple applications, multiple VMs, or multiple users share the same storage device, you need to control latency and quality of service carefully. If performance becomes unpredictable, it can affect the entire system.

That is why we have focused on a traffic-shaping mechanism that can prioritize and isolate workloads more effectively. We believe that kind of latency management will become a key differentiator for enterprise SSD controllers going forward.

Anton Shilov: How does that affect your roadmap for future controllers?

Alex Chou: It affects it quite a bit. Our upcoming controllers are not designed only for higher sequential bandwidth. They are also being designed for newer enterprise requirements such as OCP 2.7 compliance, stronger security, better QoS, and support for more advanced deployment models.

Anton Shilov: Are you already sampling your PCIe 6.x controllers?

Alex Chou: On the Gen6 side, our controller design is essentially complete; we have an FPGA [emulating algorithms], and we expect tape-out very soon. If everything goes according to plan, we expect first silicon back in the second half of 2026.

That controller not only supports a faster host interface, but also supports new features and requirements we see from AI infrastructure and hyperscale customers.

Anton Shilov: So, the PCIe Gen6 SSD platform is not just a speed upgrade for Silicon Motion?

Alex Chou: Correct. PCIe Gen6 obviously provides more bandwidth, but for us the more important part is that the surrounding system requirements are changing as well. Security, QoS, cloud deployment models, and AI storage architectures are all evolving at the same time, so the controller has to evolve with them.

Anton Shilov: Let us talk about the roadmap in more detail. You said the PCIe Gen6 enterprise controller is close to tape-out. What comes after that?

Alex Chou: PCIe Gen6 is the next major step for us, and the design is essentially complete. We expect to tape out very soon and, assuming [everything works correctly], receive first silicon in the second half of 2026.

But internally, we are already working beyond PCIe Gen6. PCIe Gen7 development has already started. In fact, the overall architecture for our Gen7 enterprise controller platform has already been defined. That means we are not just planning the interface speed increase; we are also defining the surrounding architecture, feature set, and deployment model that will be needed in the next generation of enterprise and AI systems.

Anton Shilov: So, SMI's PCIe Gen7 controller is no longer just a concept?

Alex Chou: Correct. PCIe Gen7 is already in active development. The current plan is to have internal samples in 2H, 2027 and to move toward production in that same general timeframe.

As controller development becomes more complex, you cannot wait until the market is ready before starting work. By the time a new interface reaches the market, the controller has to be nearly finished already. So, we are always working at least one generation ahead, and in practice often two.

Anton Shilov: As NAND becomes denser and more complex, error correction also becomes a bigger issue?

Alex Chou: That is a major part of controller development now. As NAND moves to higher layer counts and denser cell structures, the controller has to do more work to maintain reliability, endurance, and data integrity.

One of the areas we are working on is stronger LDPC. On the enterprise side, LDPC with a 16KB collaborative codeword is already used with SM8466, SMI’s first Enterprise PCIe Gen6 controller, and it is part of the roadmap because future NAND will require more robust error correction. That is one of the reasons enterprise controller architecture keeps becoming more complex generation after generation. You are no longer designing only for interface speed. You are also designing for signal integrity, power, security, QoS, error correction, and support for future NAND generations that may behave very differently from today's devices.

Anton Shilov: Will LDPC with 16KB collaborative codeword be enough for next generations of 3D NAND with hundreds of active layers?

Alex Chou: A 16KB LDPC engine already consumes a significant amount of silicon area and is quite sophisticated. For PCIe Gen7 controllers, our goal is to optimize and improve that engine from multiple angles rather than simply keep expanding it. We still need our architects to make the final call on exactly which improvements we will implement, but at this point we are more likely to refine and enhance the current design than to move beyond 16KB LDPC.

SSD controller development strategy

Anton Shilov: Speaking more generally, SSD controllers are increasingly becoming full platforms rather than just controllers, because integration matters so much. Do you expect close collaboration between controller vendors, NAND makers, and SSD manufacturers to become even more important as the industry moves to next-generation storage devices?

Alex Chou: I may not fully understand your question, but let me explain how we approach it.

At Silicon Motion, we design the controller architecture and build the firmware stack with a rich feature set. For example, we have developed our own [PerformaShape] traffic-shaping engine to improve QoS. That is the foundation of the platform.

From there, we have to look at how NAND evolves from one generation to the next. As we move from PCIe Gen5 to Gen6 to Gen7, controller performance has to scale accordingly. If you want to saturate the PCIe interface and deliver, say, 7 million IOPS today and much higher performance in future generations, you have to understand exactly where NAND is going.

That is why my team meets regularly with Samsung, SK hynix, SanDisk, Kioxia, and all other NAND vendors to review their roadmaps. Silicon Motion is part of that ecosystem, and because of those relationships, we usually get early visibility into future NAND generations and often receive early samples so we can bring up our controllers and make sure they take advantage of new NAND as quickly as possible.

That matters even more in the current supply environment. Because we work with all NAND suppliers, hyperscalers and cloud service providers can come to us and ask for a solution that is not tied to a single memory vendor. A company like Samsung naturally builds around its own NAND, but we have the advantage of being able to support multiple suppliers. That gives customers much more flexibility when supply is tight.

So yes, we have a core controller architecture and a common firmware base, but one of our strengths is that we work very closely with NAND vendors on future generations and make sure our platform can take advantage of faster interfaces, higher die counts, and new NAND capabilities as they arrive.

XL-Flash and storage-class memory

Anton Shilov: What about storage-class memory? Are there any developments there? As far as I can tell, adoption of Kioxia’s XL-Flash has been limited.

Alex Chou: That’s a very good question. I am actually going to visit Kioxia, so I should have a better sense of their plans after that. At the moment, Kioxia is essentially the only company still pushing XL-Flash, so they are trying to build something around it.

The challenge is that it is not just about the technology itself. You need a broader ecosystem to support it, and that is what makes the situation more complicated. We are watching it closely and trying to understand whether it is something we really need to support, but at this point I do not have a definitive answer. We are still evaluating it.

Anton Shilov: Have you heard anything similar from other suppliers? Quite a few memory makers used to talk about storage-class memory or similar technologies in their roadmaps.

Alex Chou: Based on what we know, not really. If you look back at last year’s Flash Memory Summit, several NAND makers were talking about higher-performance flash and storage-class-memory-like concepts. That created a lot of buzz at the time, and we looked into it, just as we have looked into XL-Flash, to understand whether there was a real ecosystem forming around it.

But there is much less discussion around those ideas now. One reason is simple: memory vendors do not really need those products at the moment because they can sell conventional NAND at very high prices and still generate strong returns.

Anton Shilov: In other words, they can just sell QLC 3D NAND and be perfectly happy.

Alex Chou: Exactly.

Anton Shilov: On the other hand, Nvidia wants storage devices capable of 100 million IOPS.

Alex Chou: Yes, that is where Storage Next comes in.

Anton Shilov: Has anyone actually come close to 100 million IOPS yet?

Alex Chou: I would say Storage Next gains many attentions. XL-Flash could be one possible approach to address that kind of requirement. But these are other options aiming to address high-performance and low latency needs.

What matters more is that Storage Next has a much stronger ecosystem behind it because Nvidia is actively driving it. There are regular meetings around it, and our architect has been involved from the very beginning. We have been tracking it closely and trying to make sure our future controller architecture can support it if and when the market materializes.

At the same time, Nvidia itself appears to recognize that 100 million or 200 million IOPS may not be realistic in the near term. The target seems to be moving closer to something like 50 million IOPS, which is more achievable. So yes, we are watching it very closely, and we are building in the flexibility to support it if needed.

In storage, having a technically interesting idea is not enough. The industry has to agree on how to use it, how to deploy it, and how to integrate it into systems. Storage Next currently has more momentum because the ecosystem behind it is much stronger.

Anton Shilov: So, you see Storage Next as more commercially relevant than storage-class memory, at least for now?

Alex Chou: Yes. At least today, Storage Next looks more immediate and more actionable.

We are already participating in those discussions and thinking about what future controller requirements will look like in that environment. That includes not only bandwidth, but also latency behavior, QoS, and the role storage plays in systems where GPUs are increasingly central to the data path.

That does not mean other technologies disappear. It just means that if you ask where the market is actively moving right now, the answer is much more on the Storage Next side than on the storage-class-memory side.

Anton Shilov: So, in practice, you make sure your controller works with all relevant NAND types, while the memory vendor mainly has to make sure the media itself complies with the interface requirements?

Alex Chou: When we design a controller, we already cooperate closely with NAND suppliers. Our architects look at all of the major vendors to understand whether there are any special requirements we need to account for. Then we handle another layer of optimization in firmware to make sure we can support all of those devices properly.

If you look deeper into enterprise NAND, most products also use interface chips internally to connect large numbers of dies. Those interface chips can differ from vendor to vendor, so we need to understand their configurations as well, including die counts, planes, and other architectural details. The goal is to make sure the controller and firmware together can support all of those different combinations.

So far, our architecture has been able to support NAND from SanDisk, Kioxia, SK hynix, and the other major vendors. Even if the interface chips differ, we try to keep the overall hardware design as flexible as possible.

There are really three elements involved: the controller itself, the hardware board, and the firmware. Ideally, you do not want a completely different board design for every NAND supplier. Fortunately, the industry has standardized a lot of the pinouts and module interfaces, which makes it possible to use a common hardware design and swap in NAND from different suppliers with the right firmware support.

We spend a lot of time making sure we can support all of those different combinations.

Anton Shilov: So you are effectively building controllers with a fairly clear view of what future NAND generations will look like.

Alex Chou: Exactly. We want to make sure that when the next generation of NAND arrives, we are ready to support it as broadly as possible.

ChangXin Memory Technologies (CXMT), China's largest DRAM maker, is on track to match Micron's production capacity in 2026, if Citrini Research's forecasting models are correct. If this happens, China will become the world's second-largest DRAM production base in the coming years.

The bottom-up model estimates that CXMT will finish 2026 with approximately 350,000 wafer starts per month (WSPM) of DRAM capacity, which is just 25,000 WPM less than Micron. According to the analysis, the federal government is pushing CXMT to share its DRAM technology with JHICC, Swaysure, and YMTC's subsidiary XMC to ease domestic shortages. All three companies have either built DRAM capacity already, or will do so in the short-term future, the report claims.

Swaysure has completed construction of a 140,000-WSPM fab in Shenzhen, while JHICC's Jinjiang complex contains enough cleanroom space for 120,000 WSPM, and the initial 60,000-WSPM phase is expected to receive equipment by the end of 2026. YMTC is also projected to operate about 50,000 WSPM of DRAM production at Wuhan Fab 3. If all these facilities initiate operations in the coming years, then China will have a total DRAM capacity of 600,000 WSPM (not counting Samsung's and SK hynix's fabs in China), which is dramatically lower compared to South Korea, but ahead of Japan, Taiwan, and the U.S. combined.

But China is not going to stop developing its DRAM industry, and by 2030, its total capacity will increase to around 1.41 million WSPM, according to Citrini. CXMT alone is projected to build new production capacities in Beijing, Hefei, and Shanghai, to expand its production capability to 950,000 WSPM in 2030, assuming everything goes as planned.

The supply model assumes that about 400,000 WSPM of CXMT output will remain on D1a, another 400,000 WSPM will migrate to D1b, and roughly 150,000 WPM will produce D1c devices.

Enough fab tools?

Citrini admits that producing China's outlook is considerably more difficult than predicting the development of established DRAM makers. On the one hand, there is rapidly expanding fabrication infrastructure in China, abundant state-backed financing, and government-directed technology transfers. On the other hand, among the key near-term limitations remains lithography equipment availability, particularly if the proposed MATCH Act restricts sales of advanced immersion DUV tools to select Chinese companies.

However, the author expects SMEE's domestic immersion DUV scanners to enter volume production around late 2026 or early 2027 following beta testing, as well as SiCarrier/Yuliangsheng introduce its own production-ready DUV platform in 2028. Perhaps a bit optimistically, the analysts predict that availability of lithography tools is not expected to constrain Chinese production beyond 2028, at least for mature logic and DRAM nodes. Yet, for obvious reasons, if the MATCH Act works as planned and disrupts supply of advanced immersion DUV tools to DRAM makers, production capacity expansions will not occur in the next couple of years, the report suggests.

Still, both SMEE and SiCarrier will need time to ramp up production of their lithography systems, whereas DRAM makers must learn how to use them efficiently, so we would not be as optimistic as the authors and would not expect Chinese tools to produce meaningful DRAM volumes before the early 2030s. Still, the key takeaway here is that China is on track to become a major DRAM maker rather sooner than later.

Unprecedented demand

Citrini Research projects total DRAM demand to reach 157.5 exabytes (EB) per year by 2030, including 75 EB of commodity DRAM for agentic AI CPUs, 25 EB of commodity DRAM for conventional cloud servers, 20 EB of commodity DRAM for client devices, and 37.5 EB of HBM4E as well as HBM5 for AI accelerators (15 EB and 22.5 EB, respectively).

Meanwhile, Citrini expects the whole industry to only produce around 37.5 EB of HBM4E/HBM4 memory (mostly by Micron, Samsung, and SK hynix) as well as 91.3 EB of commodity DRAM (including output in China) in 2030, leaving a deficit of 28.7 EB, or roughly 25%.

That said, the rapid expansion of DRAM production in China could be the industry's best hope to maintain relatively low prices of memory, something that will be particularly beneficial for the market of consumer devices that are sensitive to memory prices, analysts from Citrini believe. Yet, the author argues that most of this new capacity would satisfy China's own demand rather than eliminate the global shortage. Furthermore, even if companies like CXMT can expand their fabs faster, that additional capacity will mostly be consumed by domestic needs, according to Citrini.

It should be noted that to make more memory, DRAM makers need more fab tools, primarily 193nm immersion scanners. Yet, companies like ASML, Canon, and Nikon cannot increase output of immersion DUV systems quickly as these are extremely complex machines containing tens of thousands of parts. While Chinese memory companies certainly pin their hopes on local producers like SMEE and SiCarrier, neither has delivered a single commercial immersion system, and after they do, it will take them years to ramp up production of such tools.

Intel this week announced that it will invest €5 billion ($5.7 billion) to expand and modernize its manufacturing operations at the company's facility near Leixlip, Ireland. The project is intended to increase production capacity for Intel Xeon 6 processors and next-generation Intel Xeon products built using the Intel 3 fabrication process (3nm-class), as well as advanced research and development (R&D) activities at the site.

The upgrade of the facility will involve installation of new tools presumably at Fab 34 as well as extensive infrastructure improvements designed to increase manufacturing efficiency. One of the key elements of the project is the expansion of the campus' automated material transport network, which will connect separate manufacturing modules into a single high-speed production system. Meanwhile, the modernization will not involve cleanroom expansion. Intel expects the upgrade to enable the Leixlip site to produce larger volumes of Intel 3-based products and make better use of the existing cleanroom capacity.

Intel opened its Fab 34 near Leixlip, Ireland, in 2023 and has been making various chips — including Core Ultra 100-series using Intel 4 and Xeon 6 using Intel 3 production node — using its process technologies that rely on EUV lithography at the site. At present, Intel's Fab 34 is Europe's only high-volume semiconductor production facility that uses EUV tools.

In mid-2024, Intel announced the €10.1 billion sale of a 49% stake in Fab 34 with Apollo Global Management as it badly needed money. This April, the company announced that it would repurchase the 49% stake in Fab 34 for $14.2 billion, which opened doors to the current expansion and investment. Intel claims that it kicked off execution of the project earlier this year, though it did not disclose when the upgrades will be completed.

"By investing in our existing fabs with state-of-the-art technology and installing cutting-edge tools, we are not just increasing output of critical products like Xeon 6 and next gen Intel Xeon processors built on Intel 3, we are ensuring that Ireland remains at the forefront of the world's most advanced manufacturing ecosystems, while strengthening the region’s role in the global technology landscape," said Naga Chandrasekaran, Executive Vice President, Chief Technology and Operations Officer and General Manager of Intel Foundry.

Among other things, Intel says that the investment will strengthen Europe's semiconductor supply chain and support the European Union's technology sovereignty objectives by increasing domestic production of leading-edge CPUs. There is a catch about that claim, though. All the silicon produced in Ireland is transported back to the U.S. for testing and assembly, as well as makes the end products, such as Core Ultra or Xeon 6, 'made in America.'

Tesla's AI5 chip is about to enter mass production at Samsung Foundry using the company's 2nm-class process technology, a principal engineer at Samsung Foundry disclosed in a LinkedIn post, as noticed by Sawyer Merritt. As it turns out, the chip has been taped out recently.

"The Tesla-Samsung Al5 chip has reached tape-out," James Kim, a principal engineer at Samsung Foundry, wrote in the LinkedIn post. "It is scheduled to be manufactured at the Taylor fab using our latest 2nm process and will soon be integrated into Tesla's newest products. It has been an honor to collaborate with the outstanding engineers at Tesla Palo Alto and Austin over the past several months."

Elon Musk demonstrated the first sample of Tesla's AI5 in mid-April and revealed that the processor will be concurrently made both at TSMC and Samsung Foundry. Apparently, AI5 implemented in a TSMC process technology reached taped out several months ahead of AI5 implemented using a Samsung Foundry.

Tesla’s AI5 processor module that Elon Musk demonstrated in April integrates a relatively compact accelerator die — roughly half a reticle in size, based on Musk's earlier remarks — alongside 12 SK hynix memory packages that appear to be standard GDDR6 or GDDR7 devices. The package relies on an organic substrate, and the memory components are labeled similarly to conventional discrete DRAM chips.

Tesla has not revealed the width of AI5's memory subsystem, but the presence of 12 memory packages points to a relatively broad external memory interface. Assuming the module indeed uses 12 GDDR6 or GDDR7 ICs, the processor would feature a 384-bit memory bus. Depending on the memory technology and transfer rates employed, this would translate into memory bandwidth ranging from 768 GB/s all the way to 1.536 TB/s.

The company has not disclosed AI5's peak compute performance, or other detailed performance specifications, but Musk has previously claimed that, in certain workloads, AI5 can deliver performance improvements of up to 40X compared to its predecessor.

Musk expects AI5 to be one of the most produced chip ever, which is why Tesla plans to use two foundries to make it. AI5 is projected to be used in Tesla cars, Tesla robots, and in Tesla's data centers.

SK hynix, TetraMem, and researchers from the University of Southern California have developed a memristor-based in-memory computing (IMC) system-on-chip (SoC) for AI edge devices. The device is designed to accelerate neural network inference in lightweight AI models while consuming a fraction of the power that higher-end GPUs or NPUs would. To a large degree, the SoC is a proof-of-concept chip, as its performance would peak at around 2.54 TOPS in a theoretical best-case scenario, which is 16X below Microsoft's Copilot+ requirements.

A DWC-optimized IMC architecture

Memristor-based in-memory computing (IMC) accelerates neural networks by performing analog computations directly inside memory arrays, which reduces data movement and power consumption. However, depthwise convolution (DWC) — a core operation in lightweight networks such as MobileNet — performs independent per-channel filtering with limited data reuse and therefore maps poorly onto conventional crossbar arrays. To address this limitation, researchers from SK hynix, TetraMem, and USC developed an SoC that features both conventional IMC crossbars and a memristor-based IMC architecture specifically optimized for DWC.

The jointly developed SoC is based on an embedded RISC-V processor that schedules workloads and features 10 neural processing units (NPUs). One NPU out of 10 is dedicated to depthwise convolution, while the remaining nine execute pointwise and dense operations. Nine out of 10 NPU include a 256 × 256 memristor crossbar that performs the analog vector-matrix multiplication (VMM), 256 8-bit DACs that convert digital activations into analog voltages, 256 8-bit ADCs that convert the analog outputs back into digital values, and additional peripheral circuitry for reading, writing, programming, and controlling the crossbar.

The DWC-optimized NPU replaces its conventional array with eight specialized 252 × 28 zig-zag crossbar blocks, but retains DACs and ADCs. SK hynix developed and fabricated the memristor devices and integrated the resistive switching cells on top of the 65 nm CMOS circuitry using its back-end process.

That DWC-optimized NPU is the key feature of the whole SoC. To accelerate depthwise convolution, TetraMem replaced the straight selection lines used in conventional 1T1R crossbars with a zig-zag topology. As a result, the NPU contains eight 252 × 28 crossbar blocks whose diagonal selection lines activate 252 memory cells across 28 columns, which enables 28 independent 3 × 3 convolutions to run in parallel while using 100% of the array for weight storage. The remaining nine NPUs retain conventional 1T1R crossbars for 1×1 pointwise and dense layers and preserve the throughput and energy efficiency of traditional in-memory computing.

Great efficiency, low performance overall

To demonstrate the architecture, the researchers deployed a customized MobileNetV1Small neural network for the Visual Wake Words benchmark. The network contains approximately 36,000 parameters; all depthwise layers were mapped to the dedicated NPU, and pointwise layers were mapped to the remaining NPUs.

Because the memristor-based IMC hardware natively performs unsigned analog vector-matrix multiplication, inputs and weights are quantized to unsigned 8-bit values before execution. Since each memristor device can be programmed with only slightly more than 2 bits of effective precision, the design uses a two-subarray compensation technique that boosts effective weight precision to roughly 4 bits.

Conceptually, the approach is somewhat analogous to Nvidia's NVFP4 philosophy, in that both seek to achieve higher effective precision from low-precision hardware. However, the implementations are fundamentally different: NVFP4 relies on a digital floating-point representation and scaling factors, whereas the memristor SoC improves precision by compensating for analog programming errors using two programmed subarrays.

When it comes to accuracy, the SoC achieved an end-to-end inference accuracy of 80.36%, which matches the corresponding 4-bit software model. As for performance, the SoC delivers a peak throughput of 0.254 TOPS per NPU and reaches an energy efficiency of 21.3 TOPS/W at 100 MHz and 11.9 TOPS/W at 400 MHz. According to the authors, this compares favorably with published SRAM-based compute-in-memory accelerators despite being manufactured on an older 65 nm process. The SoC also exceeds Nvidia's A100 INT8 energy efficiency by an order of magnitude, the joint paper claims. Yet, these claims are largely unsubstantiated.

First up, the MobileNet demonstration does not even use all 10 NPUs. It uses one dedicated DWC NPU, five standard NPUs for pointwise layers, and leaves four standard NPUs idle. The demonstration thereby does not reveal total SoC throughput (TOPS), sustained throughput running a real network, and throughput with all 10 NPUs simultaneously saturated. In fact, the paper does not even reveal whether all 10 NPUs can be used at the same time. To that end, the 2.54 TOPS figure we mentioned earlier in the story is highly theoretical.

Validated approach

SK hynix, TetraMem, and researchers from the University of Southern California have developed a memristor-based IMC SoC featuring a novel depthwise convolution accelerator that improves crossbar utilization for lightweight AI workloads. The partners have managed to fabricate it using an outdated 65nm process technology and make it work, achieving a 21.3 TOPS/W energy efficiency and inference accuracy comparable to a 4-bit software model despite the fact that memristors can be programmed with a circa 2-bit accuracy. While the architecture validates that the approach works, the paper does not disclose the full performance of the SoC, and it is not clear whether the chip's 10 NPUs can be saturated at all.

Japanese chipmaker Rapidus will try to lure customers away from TSMC not only by offering a different kind of service, but also by offering its manufacturing services at lower prices, chief executive Atsuyoshi Koike announced this week. The company's plan to rival TSMC in terms of pricing appears on the surface as a risky move, as the company moves to develop leading-edge process technologies.

At present, Rapidus is looking at charging ¥3 million – ¥3.5 million ($18,550 - $21,635) per wafer processed using its 2nm-class fabrication process, which is significantly below TSMC's rumored quote of around $30,000 per N2 wafer, and is comparable to what Samsung is rumored to offer with its SF2 manufacturing technology, set at $20,000 per-wafer. Actual prices will depend on exchange rates, though Rapidus' general idea of offering significantly lower quotes than TSMC is immediately apparent.

Rapidus plans to start high-volume manufacturing (HVM) using its 2nm-class fabrication technology by the second half of 2027. The ramp of a new fab will take some time, so expect meaningful volumes from Rapidus to only be produced in 2028, when TSMC's N2 will no longer be its leading-edge node.

By the time Rapidus starts HVM at its IIM-1 in 2027, TSMC will have ramped production of chips using its performance-enhanced N2P manufacturing node, and the company will also absorb all the yield learning with gate-all-around the company will have with its N2 present at five fab modules. Furthermore, by the time Rapidus reaches meaningful volumes at IIM-1 in 2028, TSMC will have ramped up production using its advanced A16 fabrication process with Super Power Rail backside power delivery as well as a 3^rd-generation 2nm-class node named N2X.

In addition to the vast 2nm-capable capacity and process maturity that should be kept in mind when comparing Rapidus with TSMC, there is another factor to consider. One of TSMC's major advantages over its rivals is its Open Innovation Platform (OIP) ecosystem, which includes comprehensive electronic design automation tools, silicon-proven IPs, even for the latest nodes, a host of contract chip designers, and advanced packaging services not only from TSMC but also from its partners. For now, neither Rapidus nor Intel and Samsung Foundry can offer anything close to TSMC's OIP.

Given the advantages that TSMC will likely have over competitors with its 2nm-class fabrication technologies in 2028, lower pricing may be among the few ways to compete against the world's largest foundry. Rapidus' strategy of offering lower quotes while operating a single fab does not seem like the best way of earning money, but perhaps a certain way to lose it.

However, Rapidus may have another ace up its sleeve with single wafer processing across all process steps. The approach will greatly speed up the production cycle, which will be its indisputable advantage over other chipmakers, albeit at the cost of tool usage efficiency. Will lower quotes and shorter production cycles be enough for Rapidus to win customers from TSMC? Only time will tell.

Rapidus is reportedly negotiating with more than 60 potential customers, mainly overseas companies, which demonstrates the company's ambitions to become a viable rival to the global leader TSMC as well as contract chipmakers Intel Foundry and Samsung Foundry.

Samsung is reportedly sampling its dedicated AI processor for next-generation AI PCs with leading PC makers, such as HP and Lenovo. The chip, codenamed Gaia, was developed by the company's System LSI business unit, and it is designed to offload AI-related workloads from the CPU and GPU, reports Chosun.

Samsung's Gaia is designed to accelerate generative AI workloads on PCs and is made using the company's 4nm-class fabrication process. The chip, which is essentially a neural processing unit (NPU), is currently being evaluated by HP in the U.S. and Lenovo in China to verify its performance and evaluate whether it makes sense to integrate Gaia into their systems due in late 2027 or early 2028.

The report does not detail how Gaia differs from NPUs that are integrated into AMD's Ryzen, Intel's Core, or Qualcomm's Snapdragon X processors as well as whether it can offer significant performance advantages. Meanwhile, the report implies that the NPU (or perhaps its derivatives based on the same architecture) could be used for Samsung's next-generation implementations of its processing-in-memory (PIM) technology.

Samsung's original PIM was designed to embed compute logic directly within the HBM memory array and reduce data movement between HBM memory modules and host processors. PIM was aimed to accelerate select workloads, but did not take off because AI and HPC GPUs became very efficient and were supported by mature ecosystems, unlike PIM.

Perhaps if Samsung's upcoming Gaia NPU gains support from hardware makers and ecosystem partners, then this will give a boost to Samsung's next-generation PIM implementation as well. However, standalone NPUs and PIM are so fundamentally different that we can barely imagine that they can share a common architecture. Yet, PIM logic can be a subset of an NPU in terms of supported instructions and data formats and they can certainly share a common software framework.

One of the interesting things to note about Gaia is that it was reportedly developed by Samsung's LSI division, the same business unit at the company that is responsible for Exynos processors, automotive solutions, connectivity chips, ISPs, DSPs, display drivers, and image sensors. Given the multi-faceted nature of Samsung's LSI unit, as well as its strategic importance for the company, Samsung must be pinning some hopes on Gaia.

We have contacted Samsung and asked for a comment about the report, but we yet have to hear back from the company.