Jensen Huang, chief executive of Nvidia, denied reports about delays of the company's next-generation AI platform and said that production volumes of the upcoming Vera Rubin platforms are 'giant.' He didn't address reports about delays of Vera Rubin Ultra-based rack-scale systems carrying 144 AI GPUs.

"[The reports about Vera Rubin delays are] not true," Huang told reporters on the sidelines of an event in Japan, reports Bloomberg. "Vera Rubin is already in production. Giant amounts of production incoming."

Nvidia confirmed production of its Vera Rubin platform in January and then sampling in February, so the current comment reiterates what we already know. Nvidia stressing that 'giant amounts of production' are incoming is meant to reassure investors that the company is on track to sell a boatload of its next-generation Vera CPUs, Rubin GPUs, and Vera Rubin NVL72 systems in the coming quarters, which means more record-setting quarters.

What Huang did not address — or perhaps he wasn't asked — is Nvidia's rumored delay of its Kyber NVL144 rack-scale solution with copper interconnects due to the system's complex PCB midplane by more than a year from 2027 to 2028. An alternative dual-rack design has reportedly been canceled and an even larger CPO-based NVL576 configuration may also face delays or limited availability, the same report from SemiAnalysis claimed earlier this month. The setback could leave Nvidia's Rubin Ultra platform with a smaller NVLink scale-up domain than originally envisioned. Nvidia says its roadmap is intact.

The Kyber NVL144 architecture was designed to connect 144 Rubin Ultra GPUs using a copper-based NVLink 7 scale-up fabric, so the machine required a sophisticated PCB midplane to carry high-speed electrical links between the system's components. SemiAnalysis claims that this midplane was challenging to manufacture, leading to a delay. The report does not identify defective chips or problems with particular components mounted on the board, but specifically points to the manufacturability of the PCB infrastructure itself.

"Our roadmap is intact," a spokesperson for Nvidia told Tom's Hardware.

Nvidia's statement on the matter neither confirms nor denies the report, but indicates that the company will be able to offer products mentioned in its roadmap without revealing whether they also remain on their previously announced launch schedules.

Nvidia reportedly considered another copper-based design, called NVL72x2, as an alternative to Kyber. The system would have placed two Oberon racks back-to-back to expand the size of the NVLink scale-up domain without using optical interconnects. However, SemiAnalysis says customers rejected the unusual design and operational requirements, but does not specify their individual objections that could include serviceability, cooling, cabling, and data-center layout.

Meanwhile, the planned NVL576 rack scale solution that was supposed to combine eight Oberon racks interconnected using co-packaged optics between NVSwitches has also been postponed, or shipped in relatively small quantities because of 'ongoing CPO challenges,' SemiAnalysis claims.

The existence of the planned NVL576 configuration suggests that Nvidia had been developing some form of CPO-enabled NVSwitch connectivity for the Rubin generation. In theory, similar optical switch-to-switch connectivity could potentially be used to join smaller GPU groups into an NVL144 system and bypass Kyber's problematic copper midplane. However, the available information does not clearly indicate whether the CPO technology intended for NVL576 could reproduce Kyber's topology, bandwidth, and latency characteristics, or whether it was sufficiently mature for high-volume deployments by potential NVL144 customers.

The reported Kyber delay comes on the heels of another report saying that Nvidia had canceled quad-compute-chiplet version of its Rubin Ultra in favor or a dual-compute-chiplet design that is projected to deliver 2X lower performance. With Kyber NVL144 delayed and NVL72x2 cancelled, Nvidia will only be able to offer 72-way scale-up systems till sometimes in 2028, meaning that AMD and Google may end up with more competitive scale-up systems in 2027 – 2028. AMD's Mega Pod based on the Verano CPUs and Instinct MI500-series accelerators, is expected to pack up to 256 accelerators. Google's TPU 8i can provide roughly 1,024–1,152 accelerators within one low-latency domain, whereas the TPU 8t goes much further and can get to 9,600 chip packages per domain.

Intel has entered high-volume manufacturing using ASML's High NA extreme ultraviolet (EUV) lithography technology for a subset of its Intel Core Ultra Series 3 "Panther Lake" processors, becoming the first company to ship high-volume logic products manufactured with the technology. ASML announced the milestone in an official press release on Wednesday, July 15, confirming that Intel Foundry is running the qualified High NA layers on its Intel 18A process node in Oregon.

According to ASML, Intel is using High NA EUV to pattern selected Intel 18A layers, with products already shipping to customers at yields matched to those achieved on ASML's existing NXE EUV platform. These layers are dual-qualified, meaning the same layer can be exposed on either an existing 0.33 NA NXE scanner or a 0.55 NA EXE scanner, with the resulting wafers being interchangeable.

High NA EUV has long been viewed as the successor to today's EUV lithography, promising to extend semiconductor scaling by enabling manufacturers to print smaller, denser circuit patterns that are becoming difficult to achieve with existing tools. Until now, the platform had been confined to R&D work. ASML’s announcement marks the first time High NA EUV has been used to produce and ship a high-volume commercial logic product.

Panther Lake, built on the Intel 18A manufacturing process, is spearheading this transition. Rather than replacing the company's entire lithography flow, Intel is applying High NA EUV to specific layers while the remainder of the chip continues to be manufactured using conventional lithography.

High NA EUV builds on the same 13.5-nanometer extreme ultraviolet light used by today's scanners but increases the optical system's numerical aperture (NA) — how much light a lens system can collect and focus onto a silicon wafer — from 0.33 to 0.55. The higher value resolves finer features in a single exposure, allowing chipmakers to print smaller patterns with greater precision and process control.

This increased resolution is expected to reduce reliance on complex multi-patterning techniques for some of the industry's most demanding layers, thereby simplifying manufacturing and improving feature fidelity. In the long term, these capabilities are expected to support higher transistor densities and improved performance in future processors, particularly as AI workloads continue driving demand for increasingly advanced semiconductor technologies.

"With increased resolution and better process control, the introduction of High NA EUV marks a substantial development in semiconductor lithography," said ASML President and CEO Christophe Fouquet. "We are proud to play a role in enabling the smaller, denser patterning that will accelerate advancements in AI and other emerging technologies."

Intel and ASML have been working towards this milestone for several years. In 2024, Intel completed installation of one of the industry's first commercial High NA EUV lithography systems, the TWINSCAN EXE:5000, at its Hillsboro, Oregon, research and development facility. The company later became the first to qualify ASML's second-generation TWINSCAN EXE:5200B, which increases wafer throughput and overlay accuracy while incorporating an improved EUV light source over its predecessor.

While the announcement represents High NA EUV's commercial debut, it does not mean Panther Lake is manufactured entirely using the new lithography platform. Instead, Intel has qualified High NA for selected layers, an approach that mirrors how new lithography generations are typically introduced into advanced semiconductor production before broader adoption across future nodes.

Intel Foundry Executive Vice President and General Manager Naga Chandrasekaran said that qualifying the High NA process option on selected Intel 18A product layers enables the company's existing tool fleet to deliver higher manufacturing output while providing flexibility for future process technologies.

Panther Lake itself is not a future product. Intel launched Core Ultra Series 3 at CES on January 5, 2026, opened preorders the following day, and put systems on shelves globally from January 27. The Core Ultra X9 378H followed in April alongside the value-tier Core Series 3, code-named Wildcat Lake, and the handheld-focused Arc G3 parts arrived on May 28.

The announcement’s statement that the product is shipping to customers refers to wafer flow from the fab into the supply chain, rather than to a product launch. ASML says the two companies will continue working on High NA readiness, with the flexibility to incorporate the technology into future nodes based on customer needs — most immediately, Intel 14A, which Intel has designed to use High NA on a set of its tightest-pitch layers.

Google plans to use Intel's EMIB-T packaging for its next-generation TPU codenamed Humufish, according to SemiAnalysis. TSMC's portfolio of chip-on-wafer-on-substrate (CoWoS) technologies has become the de facto standard advanced packaging option for nearly all AI and HPC processors made in the industry. Competing offerings are usually considered as secondary solutions if CoWoS is in tight supply, but things are beginning to change.

Google is a long-standing CoWoS customer for TPUs, starting from the Third-Generation TPU, all the way to Google's latest Eighth-Generation TPUs. Assuming that SemiAnalysis's report about Google's decision to move to EMIB-T with its Ninth-Generation TPUs is accurate, it's a big decision for Google, as switching from one advanced packaging technology to another is a complicated endeavor, which involves plenty of changes and unknowns. Understanding Google's reasons for the switch could shed some light on the prospects of Intel's and TSMC's advanced packaging technologies, which will be used by leading chip designers and hyperscalers in the coming years.

Advanced packaging technologies at glance

For years, Google used TSMC's CoWoS-S, and later, CoWoS-L packaging. Initially, the company used CoWoS-S packaging, which relies on a silicon interposer up to 3.3X the reticle size, but with its 7th- and 8th-Generation TPUs, the company moved to CoWoS-L. CoWoS-L relies on a redistribution layer (RDL) interposer with embedded local silicon interconnect (LSI) bridges that enable high-performance die-to-die links, which can scale packages to 5.5X the reticle size today. TSMC promises to improve CoWoS-L's capabilities to scale over 14X the reticle size by the end of the decade.

Unlike CoWoS, Intel's embedded multi-die interconnect bridge (EMIB) technology does not use any interposers. The technology instead relies on tiny embedded silicon bridges within the substrate to enable high-density die-to-die interconnections, whereas everything else is routed through an inexpensive organic substrate.

EMIB-T adds through-silicon vias (TSVs) to the bridge, which enables power to flow vertically instead of going through the organic substrate. In addition, Intel's EMIB-T also integrates sophisticated metal-insulator-metal (MIM) capacitors and a dedicated ground plane into the bridge to improve power integrity. The latter is a particularly important feature of complex next-generation AI accelerators, which demand more, cleaner power, and for which power delivery is becoming as challenging as signal routing.

The main selling point of EMIB (and EMIB-T) is that it is not constrained by interposer reticle limits as it places small silicon bridges only where high-density die-to-die links are needed. Strictly speaking, CoWoS-L is not either, as it uses LSIs locally as well. The difference is that those bridges are embedded into a package-wide RDL interposer that connects everything and enables dense interconnections across the package.

Since both CoWoS-L and EMIB-T are designed to address the same applications and have many similarities in the way they do this, the choice between them is likely driven by a combination of factors rather than one single advantage or disadvantage. On the technology side of matters, these factors include interconnect performance and density, power delivery, scaling beyond very large package sizes, and mechanical rigidity. On the business side of things, costs, capacity availability, and supply chain diversification are also a significant factor.

Crucial differences

SemiAnalysis claims that the main advantage of EMIB/EMIB-T over CoWoS is the lack of reticle limit, but this argument does not fully hold against CoWoS-L, as it was invented specifically to escape the reticle limitation by replacing the monolithic silicon interposer with localized LSI bridges.

When it comes to dense, package-wide routing, CoWoS-L's RDL interposer is fundamentally superior to an ordinary organic substrate offered by EMIB-T. Organic substrate wiring has coarser line/space dimensions and larger vias, so it cannot provide the same routing density as CoWoS-L's fine-pitch RDL. Where an EMIB bridge connects adjacent dies, Intel can achieve very high interconnect density. But anything that needs to travel beyond those bridges must use the package substrate or cross a topology involving additional bridges.

By contrast, CoWoS-L gives the designer two levels of connectivity: LSIs provide extremely dense local die-to-die connections, while the global RDL interposer provides relatively dense and flexible routing across the entire package. This means the RDL can carry longer, lower-density connections without consuming valuable LSI resources, while still offering much finer routing than the underlying package substrate.

One scenario for Google's choice is that it potentially wanted better power delivery than what CoWoS-L could offer. EMIB-T integrates TSVs for vertical power delivery, sophisticated MIM capacitors for local decoupling, and a dedicated ground plane into its silicon bridges. The combination of these features substantially reduces power-delivery impedance and improves transient response and power integrity, which gives EMIB-T a major advantage over conventional EMIB for power-hungry AI accelerators. However, we have no idea how EMIB-T stacks up against CoWoS-L in the case of Google’s Humufish.

Of course, the larger the RDL interposer becomes, the greater its parasitics can become, potentially limiting scaling unless TSMC finds ways to mitigate them. However, EMIB does not eliminate long-distance wiring: If two distant dies must communicate, those signals still have to travel somewhere, and routing them through an organic substrate is not inherently electrically superior to routing them through a purpose-built RDL interposer. Therefore, it is difficult to claim that Google chose EMIB-T over CoWoS-L, simply because EMIB-T offers superior package-wide electrical characteristics.

After Nvidia suffered yield loss with its Blackwell data center GPUs due to an alleged mismatch in the coefficient of thermal expansion (CTE) among the GPU chiplets, LSI bridges, RDL interposer, and motherboard substrate, which led to warping and system failure, it is reasonable to question the mechanical rigidity of CoWoS-L packages. Nvidia has found a solution for its dual compute chiplet Blackwell packages, and so have other developers of AI accelerators. However, as package dimensions increase, they may behave differently, therefore causing yield losses.

By contrast, EMIB/EMIB-T eliminates the large RDL interposer and embeds small silicon bridges in the organic substrate, so most of the package consists of the substrate itself. This does not make EMIB/EMIB-T packages immune to mechanical failures, as large packages can warp and bend, causing various problems. However, as such packages lack the very source of global thermomechanical stress, they can potentially be more robust mechanically. However, EMIB-T can potentially complicate things because TSVs, additional metal structures, MIM capacitors, and their ground plane make the bridge more complex. Thus, Intel must manage both global package warpage and local stresses around each embedded bridge to ensure the mechanical rigidity of these packages.

Ironically, while CoWoS-L can offer denser package-wide routing, which is better for ultra-large processors, EMIB-T may potentially provide better mechanical rigidity required for such devices. Nonetheless, EMIB-T and its organic substrate do not eliminate package bending or cracking risks entirely.

Economics

If Google's Humufish TPU really moves to EMIB-T, the decision could well be both technical and strategic. Google has the engineering resources to opt for an all-new packaging technology in an effort to lower costs and eliminate dependence on TSMC's constrained CoWoS capacity. Nvidia tends to procure advanced packaging allocations years in advance, so it is possible that Google could simply not get enough CoWoS-L wafers for its 9th-generation TPU.

As a bonus, Google can also build relationships with Intel Foundry without using the company's fabrication technologies. In fact, keeping in mind that Intel and Google already have a strategic agreement covering Intel Xeon CPUs, it wouldn't be too surprising to learn that the cloud giant is courting Intel Foundry as well.

Both Intel's EMIB-T and TSMC's CoWoS-L have their own technological and economic advantages and disadvantages. Perhaps the biggest advantage of CoWoS-L is its predictability, as the company has experience with that tech. However, if Google has decided to drop that predictability in favor of an all-new packaging method, it may well have a combination of technological and strategic reasons to do so.

Intel announced a €5 billion ($5.7 billion) investment on Monday to expand chip production at its Leixlip campus in County Kildare, Ireland, upgrading existing fabs to increase output of Intel 3 wafers for Xeon 6 and next-gen server processors. The program accounts for roughly 30% of Intel's planned 2026 capital expenditure of about $17 billion, adds several hundred permanent roles to a 4,900-strong Irish workforce, and is scheduled to be substantially deployed by the end of 2027. Naga Chandrasekaran, Intel's chief technology and operations officer and general manager of Intel Foundry, told Reuters that "the demand for servers, the demand for AI is driving a significant increase in the need for Intel 3 wafers."

The announcement comes just shy of a year after CEO Lip-Bu Tan cancelled Intel's planned €30 billion fab complex in Magdeburg, Germany, and a €4.6 billion assembly and test plant in Wrocław, Poland. Those cancellations came with a memo in which Tan wrote that Intel had "invested too much, too soon – without adequate demand."

The Ireland program, however, passes the test Magdeburg failed on every measure that Intel boss Lip-bu Tan set: It uses cleanrooms that already exist; it's funded from Intel's own capex with no announced state aid; and it expands an already shipping revenue product into a demand pipeline Intel says currently exceeds its supply.

What €5 billion buys

It’s understood that no new manufacturing plants are part of the program, with the money instead going to upgrades of existing fab facilities, installation of leading-edge production equipment, and an expansion of the automated track system that links the campus's manufacturing modules into a single production flow. Intel said the work began earlier this year and will employ around 2,000 specialized tradespeople during the build-out, on top of the permanent hires.

Fab 34 is the focal point of the spending, with Chandrasekaran telling the Irish Times that "Ireland is our centre of excellence for Intel 3; we are not running Intel 3 in any other Intel manufacturing facilities." The fab began high-volume production on Intel 4 in September 2023, as the first EUV facility in Europe, and it now runs both Intel 4 and Intel 3, producing compute tiles for Core Ultra parts and Xeon 6 server processors. Intel has spent more than €30 billion in Ireland since 1989, over half of it between 2019 and 2023, doubling the campus's manufacturing footprint.

The spending follows directly from a transaction Intel closed in April, when it bought back the 49% stake in the Fab 34 joint venture it had sold to Apollo-managed funds for $11.2 billion in 2024, paying $14.2 billion to reclaim it. Apollo walked away with a roughly 27% gain in under two years. Intel now owns 100% of every wafer Leixlip produces, so each additional Intel 3 wafer the €5 billion generates flows entirely to Intel's own margin, rather than being shared with an outside capital partner.

The projects Intel cancelled

Magdeburg had roughly €9.9 billion in pledged German subsidies attached when Tan killed it, and Wroclaw had €1.9 billion in approved EU state aid. Fab 38 in Kiryat Gat, Israel, remains paused, and the Ohio site has slipped to around 2030. Every leading-edge wafer Intel produces for the foreseeable future comes from three U.S. states and one Irish campus, a concentration that made Leixlip the only European site left to expand and the cheapest place anywhere in Intel's network to add advanced capacity quickly, since the shells, EUV tools, and workforce are already in place.

Intel's Data Center and AI revenue rose 22% year over year to $5.1 billion in Q1 2026, and CFO David Zinsner told analysts on the April earnings call that Intel faces "unprecedented demand for silicon," with demand exceeding supply across the company's server lines. Intel Foundry revenue grew 16% to $5.4 billion in the same quarter, but external foundry revenue was just $174 million against a $2.4 billion operating loss, so the wafers that pay for Leixlip's tools are overwhelmingly Intel's own Xeon chips, rather than customer designs. A single campus running the entirety of a revenue-critical node also concentrates risk: Any disruption at Leixlip has no second source, because Intel 3 exists nowhere else.

Europe's most advanced node, without European money

Intel 3 is now the most advanced process technology manufactured anywhere in Europe, and Chandrasekaran told the Irish Times the expansion provides "a technology sovereignty within the EU that the EU is targeting." Interestingly, no EU or Irish state aid accompanied the announcement, which distinguishes it from TSMC's €10 billion ESMC fab in Dresden, where the European Commission approved a €5 billion funding package for a plant producing 28/22nm and 16/12nm chips for automotive and industrial customers, scheduled to be operational from late 2027. Europe's only leading-edge logic production is self-funded by an American company for its own products, while its subsidized flagship project makes trailing-edge silicon.

Commercial electricity in Ireland runs up to twice the rates Intel pays in Arizona or Taiwan. Intel warned Irish ministers in August 2025 that its competitiveness was under threat from energy costs, and the company flagged up to 195 mandatory redundancies at Leixlip in mid-2025 as part of its global workforce reduction. IDA Ireland paid Intel €30 million in 2023 to offset elevated EU power bills, so that "self-funded" framing has at least one recent caveat.

Meanwhile, Intel's 14A node is being developed in Oregon; no Irish role in it has been announced, and two prospective 14A customers will decide the node's fate in commitments expected between late 2026 and early 2027. Ultimately, the €5 billion makes Leixlip the fully-loaded workhorse of a node Intel will eventually move past, not a contender for the leading edge. Whether Europe gets anything newer than Intel 3 remains to be seen.

Ukrainian FP-1 drones struck the Gazprom Neft oil refinery in Omsk, Siberia, on July 6 after flying roughly 2,500 km over more than 12 hours, halting operations at Russia's largest gasoline producer, according to a report from UK pub The Telegraph. It was the longest-range Ukrainian drone strike of the war, carried out by an aircraft built around a plywood load-bearing structure, foam wings, and a two-cylinder piston engine, at an estimated cost of $55,000 per unit.

Despite its lightweight structure, the drone managed to cause some pretty severe damage, setting fire to the CDU-10 crude distillation unit per Reuters, which handles 24,580 metric tons of crude per day and accounts for around 38% of the plant's processing capacity. A second unit, CDU-11, responsible for a further 37%, was shut down after network links vital to its operation were damaged. The refinery, which processed 22 million metric tons of crude (about 440,000 barrels per day) in 2024, stopped selling gasoline and diesel on the St. Petersburg International Mercantile Exchange the following day.

The FP-1, built by Kyiv-based Fire Point, is engineered not for sophistication or as cutting-edge drone tech, but for mass production. The airframe uses plywood structural elements and foam wings skinned in fiberglass or carbon fiber, with a twin-boom layout, a roughly five-meter wingspan, and no landing gear. A solid rocket booster launches it from a fixed platform or a truck, and a two-cylinder engine driving a propeller carries it the rest of the way.

The drone's original design range was 1,600 km with a warhead of up to 60 kg. At the Eurosatory defense exhibition in Paris last month, Fire Point showed an upgraded FP-1 with an additional fuel tank integrated into the wing, extending its range to 2,700 km. That variant put Omsk, and most of Russia's refining capacity, within reach. The Telegraph reported that the drones used in the strike were lightened, with lengthened wingspans and enlarged fuel tanks, and that Fire Point co-founder Denys Shtilerman said Ukrainian planners spent more than a week plotting a route around Russian air defenses. Navigation relies on a purpose-built algorithm designed to resist GPS spoofing, with inertial and satellite guidance layered together.

Fire Point produces around 100 FP-1s per day, and the aircraft now accounts for roughly 60% of Ukraine's deep strikes inside Russia, according to company CEO Iryna Terekh. Each drone costs less than a single interceptor missile fired by the multimillion-dollar S-400 and Pantsir batteries tasked with stopping it, and Russia simply can't field enough of those systems to cover a country spanning 11 time zones.

This design takes advantage of Russia's air defense network, which was designed to detect fast, high-flying jets and ballistic missiles, not slow, low-altitude aircraft with small radar signatures. Moscow scrambled Su-57 stealth fighters against the Omsk raid, but several drones still got through. Kyle Glen, an open-source investigator, told The Telegraph that Russia appears to concentrate its defenses around Moscow and St. Petersburg, leaving "almost nothing behind it to stop them" once drones penetrate the outer layer.

Ukraine's General Staff recorded 172 deep strikes last month, up from 85 in February, and Omsk was the sixth major Russian refinery forced to fully or partially shut down since the start of June. Last month, President Volodymyr Zelensky said that a new Fire Point drone can reach targets at 3,000 km, and the company's FP-5 Flamingo cruise missile, carrying a 1,150 kg warhead over the same distance, has begun striking Russian weapons facilities as air defenses thin out.

The Sino-American chip wars have resulted in many back-and-forth salvos and negotiations as the countries try and strike a balance between technology access and trade. Currently, both sides have set respective import and export controls, letting specific companies on a case-by-case basis. Today, Reuters reports that Chinese telecoms giant ZTE and server firm Maginfra have received U.S. approval to buy Nvidia's last-gen H200 "Hopper" chips.

ZTE joins a club that counts Alibaba, Tencent, ByteDance, and JD.com among the roughly 10-strong group of Chinese companies with U.S. clearance for those purchases. Additionally, an apparent subsidiary of Kingsoft Cloud got approval to buy AMD accelerators equivalent to Nvidia's H200, presumably Instinct MI300X-class chips.

Over on the Chinese side of the table, Reuters remarks that there's no word on whether the respective authorities will give ZTE the go-ahead for import, as the country has taken on a protectionist stance as it tries to grow its own chip industry. The country has discouraged firms from purchasing foreign tech and has instead pushed companies to acquire homegrown accelerators. Huawei in particular has made great strides both technologically and financially.

But even with those domestic production initiatives, the Chinese hunger for AI silicon is so deep that six months ago, Reuters said the nation's tech firms had more than two million H200 chips on order, far more than what Nvidia had on hand at the time. We'd venture that hunger has barely subsided.

ZTE might not be a familiar name Stateside, but the corporation is one of China's largest telecommunication conglomerates, and among many other ventures, it sells all sorts of carrier network gear that's installed worldwide, along with corresponding client-facing equipment, including phones and IoT equipment. Like most any sizable technological venture, ZTE has joined in on the cloud computing and AI push, so it needs accelerators to make those ambitions reality.

The current status of the AI chip trade situation is roughly that the U.S. allows Chinese firms to buy AI chips up to and including the Hopper family (meaning no Blackwell chips), with a 25% export tariff, though final decisions are made on a case-by-case basis. Over on Chinese shores, Beijing's authorities play their cards close to their chest and dole out approvals as they see fit, with no clear rules seemingly set. But China is, of course, a global power with trade connections to most everyone, so interested firms were able to get their hands on Blackwell chips through various creative (and potentially illicit) means.

Whether this change will actually clear the way for any great volumes of H200 accelerators to make their way into ZTE's data centers remains to be seen. CNBC cites a U.S. trade official who today stated that "very few shipments against licenses for H200s and equivalents have taken place. It’s a very small quantity of chips" during a congressional hearing. If H200 shipments become material to Nvidia's bottom line, we'll almost certainly hear about it in future comments or earnings reports.

Elon Musk's Colossus 2 xAI data center, which runs independently of the power grid through on-site natural gas turbines, is said to be releasing thousands of tons of nitrogen oxide and carbon monoxide every year. According to Reuters, the company has installed 59 temporary, mobile natural gas turbines without permission, and these unpermitted portable units mostly heavily affect the communities surrounding the site, which happen to be predominantly black and are already suffering disproportionately high lung disease rates. xAI has claimed that it’s running 27 turbines without any permits, saying that it’s exempted because of their temporary nature.

Elon Musk’s alleged use of illegal turbines isn’t a new issue, with the community discovering that it’s been using over 30 gas turbines on the site, despite only having an ongoing application for 15 in July 2025. The company said that these turbines are exempted from the permitting process, as they are not permanent installations and will be moved within 364 days. The Environmental Protection Agency (EPA) issued a ruling earlier this year that removed all exceptions, but told Reuters that “it’s considering changes allowing ‘regulatory flexibilities’ for portable units while continuing to protect public health.”

The Colossus data centers were put up in record time, and Musk had to bring his own energy sources to achieve this. That’s because connecting to the grid could take years, especially if the grid must be upgraded to deliver his 1-GW capacity target. However, the Clean Air Act permitting process could take a similarly long time, with the report suggesting xAI bypassed it completely just to achieve its goal. Adding to the complexity, while the data center is located in Tennessee, Reuters reports that "at least" 57 of the 59 turbines are actually located just over the state line in Mississippi, which issued a permit for 41 permanent turbines in March. xAI and Mississippi environmental regulators claim the turbines are mobile and therefore don't need permits, but they also aren't covered by the permit for 41 permanent turbines.

This did not sit well with the communities surrounding the data centers, especially Colossus 2, which sat near the border of Tennessee and Mississippi. Because of this, xAI (now called SpaceXAI after its recent merger with Space X) is facing a lawsuit from the NAACP, which alleges that the operation of these unpermitted turbines resulted in an 111% increase in nitrogen oxide exhaust, an 83% increase in PM2.5 airborne particles, and an 88% increase in formaldehyde emissions. The Reuters investigation says that just 30 of the 59 turbines listed could emit 2,500 tons of nitrogen oxide, 4,000 tons of carbon monoxide, and 22 tons of formaldehyde annually — way above the 100-ton nitrogen oxide threshold that the Clean Air Act set for turbines to operate without a permit.

These pollutants are proven to have adverse effects on the health of the people living within a five-mile radius of the source, and census data showed that the residents living in the affected area are predominantly black. Since Colossus 2 straddles a state boundary, the publication listed the data for two counties — DeSoto County, Mississippi, and Shelby County, Tennessee. Statistics show that about 46% of the population in the former and 94% in the latter are black, which is significantly higher compared to the 33% and 52% in the rest of the counties.

While the report did not say that these communities were deliberately targeted, it also pointed to a 2022 study that showed that areas once redlined by banks still suffer in the present day from higher air pollutant emissions. SpaceXAI recently announced an automatic 50% discount and free hardware rentals on Starlink plans for people living near Colossus 1 and 2, with SpaceX VP for Starlink Michael Nicolls saying on X, “The unique capabilities of the Colossus datacenters could not be accomplished without the partnership and support from the local Memphis community.” While this may bring some benefit to already existing Starlink users, some say that this is merely a PR stunt to help give the company a better image as the community is battling the air and noise pollution they bring to the area.

China exported 179.44 billion integrated circuits worth $177.28 billion in the first six months of 2026, an increase of more than 96% year on year by value, according to data released by the country's General Administration of Customs and reported by the South China Morning Post. The figures are Beijing's own customs numbers, presented at a state press briefing as part of a broader account of China's trade performance, and they made semiconductors one of the main contributors to the country's double-digit export growth over the period.

The customs administration attributed the surge to global demand for AI hardware, but the underlying numbers point more towards a worldwide memory price boom that has inflated the value of the commodity-grade chips that China exports in volume.

The half-year value figure implies an average of roughly $0.99 per exported chip, which reflects the composition of China's IC exports: memory, power management, microcontrollers, and other mature-node parts, along with chips packaged and tested in China for re-export, rather than advanced processors.

Earlier customs releases this year show the growth is being driven by prices rather than shipments. In January and February, IC export value rose 72.6% year on year while volume grew only 13.7%, according to the same customs data series. In April, export value rose 100.1% year on year, the first monthly doubling on record, as price increases across AI servers, data centers, and memory spread through the supply chain.

Samsung, SK hynix, and Micron have redirected DRAM capacity toward high-bandwidth memory for AI accelerators and are phasing out DDR4 production, tightening supply of conventional memory and pushing spot and contract prices sharply higher through late 2025 and into 2026. Chinese memory makers, including CXMT in DRAM and YMTC in NAND, sell into exactly that commodity segment, so their export quotations have risen alongside global prices. China's IC export growth ran at 24.7% through the first ten months of 2025 per DigiTimes, before accelerating to the 70% to 100% monthly rates recorded this year, a timeline that tracks the memory price cycle, not any step change in Chinese output.

Volume growth is real, however, if far smaller than the value figure suggests. China produced 484.3 billion ICs in 2025 and counted 3,901 domestic chip design companies with combined sales up nearly 30% year on year, as a years-long buildout of mature-node fab capacity reached scale and exports became the outlet for output exceeding domestic demand.

It’s worth noting that a meaningful share of China's IC exports is processing trade, in which chips are imported, packaged or tested at Chinese OSAT facilities, and re-exported. These are counted in customs figures as gross value crossing the border, not domestically designed and fabricated silicon, and are therefore somewhat misleading,

Adjacent categories showed the same AI-driven pattern, with exports of automatic data processing machines and parts, a category covering computers, servers, and memory modules, rose 41.3% year on year to $138.08 billion in the first half. Industrial robot exports rose 18.6% to 6.29 billion yuan ($927.7 million) across 141 countries and regions.

As China reports record export figures, U.S. policy continues to shift. A Bureau of Industry and Security rule that took effect on January 16 moved license applications for Nvidia's H200 to case-by-case review for Chinese customers, and Nvidia has since booked orders for more than 400,000 units from ByteDance, Alibaba, and Tencent, though it had recognized no revenue from those orders as of March.

Beijing obviously presented the export figures as evidence of industrial strength. "The export growth was fundamentally driven by precisely matching 'Made in China' [products] with diverse global demand," Wang Jun, a vice-minister at the General Administration of Customs, said at Tuesday's briefing, as quoted by the South China Morning Post.

New York Governor Kathy Hochul signed into law Senate Bill S10642 today, also called the Responsible Data Center Development Act, which would put a one-year moratorium on all data center developments in the state. According to Reuters, this is the first temporary ban to be enforced statewide in the U.S. Maine’s legislature was actually the first one to pass a statewide moratorium, but Maine Governor Janet Mills vetoed the measure after it failed to exempt a data center project “that enjoys strong local support from its host community and region.”

"As data center development threatens ⁠to hike up utility bills, deplete our natural resources, and create uncertainty for New Yorkers, it's my responsibility to take ​action and lead," Hochul said in a statement. She also said that she’s pursuing legislation to repeal tax exemptions for large data centers. The moratorium will apply to data center projects with a capacity of 50 megawatts or more, with the New York Department of Environmental Conservation not issuing any more permits to projects that haven’t been completed yet.

Hochul said that the state will build a Generic Environmental Impact Statement (GEIS) so that future data center developments are held to “consistent standards,” while also looking at how the construction and operation of these projects will impact the environment. Although the data center moratorium is set for one year, the governor’s office said that it will be lifted once the state has finalized the GEIS.

President Donald Trump has been pushing for the development of AI technologies, with the White House releasing the ‘AI Action Plan’ to accelerate infrastructure build-out. While this policy encouraged the development of AI data centers, the numerous large projects also resulted in memory and storage chip shortages, as well as negative impacts in the communities and regions where they’re located. For example, Monitoring Analytics, which oversees the largest power grid operator in the U.S., attributes an “irreversible” 76% price hike to increased data center demand, while a Virginia county has asked government offices to conserve power because of AI-driven price hikes. There have also been multiple issues with various data center projects relating to water consumption and air and noise pollution, which is why 70% of Americans now oppose having a data center built near their home.

All this pushback has resulted in many jurisdictions passing data center moratoriums. More than 75 projects have already been delayed in the first half of this year, amounting to $130 billion, with New York state being the first one to pass a state-wide temporary ban. Before this, Seattle, which plays host to the headquarters of Amazon and Microsoft, passed a similar one-year moratorium last month.

While delays like this will likely negatively impact the future availability of compute within the U.S., it’s also forcing tech giants to speed up innovations and governments to pass laws that protect their constituents. Multiple startups have started unveiling or even turning on their small modular reactor (SMR) prototypes, which could deliver the power needed by data centers without increasing air pollution or straining the local power grid. AI tech companies like Microsoft and Nvidia are also working on solutions that will cut data center energy use and water consumption, while Oregon’s POWER Act increased data center bills by 30% while cutting residential costs by 1.3%.

• Future Games Show will return for Gamescom 2026
• The main showcase will begin on August 26, followed by the FGS Live, and the FGS Best Of Gamescom will air on August 30
• Future Games Show at Gamescom will feature world premieres, new trailers, and more

The Future Games Show will officially return next month for Gamescom 2026 with three digital showcases.

Future Games Show at Gamescom will air the same day the industry event kicks off, on August 26, and feature new announcements from "some of the industry’s most creative studios," including world premieres, exclusive trailers, developer deep dives, and brand-new game demos.

The recent Future Game Show Summer Showcase in June included 40+ games and 11 world premieres, and reached over 17.8 million live and launch-weekend views, so viewers should expect some more exciting game reveals.

FGS Live From Gamescom will immediately follow the main showcase on August 26, be hosted by the FGS editorial team, and feature more world premieres and exclusive trailers, as well as news and interviews from the Gamescom show floor.

To round out the event, the FGS Best Of Gamescom broadcast will kick off on August 30 and take viewers to the show floor to wrap up the best games of the event. Those tuning in can also expect exclusive booth tours, developer interviews, and a recap of Gamescom’s most exciting announcements.

All three digital shows can be watched on Future Games Shows' Twitch, YouTube, X, TikTok, Facebook, and GamesRadar+.

"The Future Games Show is the best place to discover new games, from indie gems like acclaimed-puzzler Blue Prince to AAA blockbusters such as sci-fi RPG Exodus," said Daniel Dawkins, Content Director of Future Games Show at Future. "Our Summer Showcase delivered 3.72 wishlists per live viewer, comfortably outperforming industry averages, thanks to our super-engaged viewers.

"Since launching in 2020, we have been proud to showcase the industry's most exciting titles alongside premier hosts like Troy Baker, Alix Wilton Regan and Ben Starr. This Gamescom, we are delivering three massive digital showcases packed with the latest news and world premieres for PC and consoles. Don’t miss it!”

AI tech giant Nvidia, which builds some of the most coveted AI chips in the world, has reportedly created a new “whitelist” of verified companies to help prevent its products from getting smuggled into China. According to the Financial Times, this roster cuts the number of authorized clients by more than half, with those remaining having passed tougher compliance inspections to ensure that they are genuine businesses, not shell companies designed to forward Nvidia GPUs and servers into China. Some of the steps that Nvidia took to help safeguard its chips reportedly included sending staff to customer data centers, contract verification, and interviewing end users.

Sources told the publication that the company made this move after Washington pressured it into tightening its legal compliance, which comes months after the arrest of Supermicro co-founder Yih-Shyan “Wally” Liaw, alongside two other suspects, for allegedly smuggling $2.5 billion worth of Nvidia hardware into China. This clampdown also extended into Singapore, which saw the seizure of a $42-million mansion tied to alleged AI GPU smugglers, and Taiwan, where authorities raided the offices of Supermicro and two supply-chain partners as part of a chip smuggling probe. Nvidia was not immediately available for comment on the news.

Although the U.S. has banned the latest AI GPUs for export into China since 2022, various investigations showed Chinese companies could still easily get their hands on these coveted chips until recently. Washington’s and its allies’ crackdown on AI GPU smuggling have cut supply in China, which is now making it harder for AI companies to procure the processors they need. President Donald Trump took a 180-degree turn in December 2025 and finally allowed Nvidia to export its H200 GPUs to select customers in the region, which would have alleviated the situation. However, Beijing refused to allow Chinese companies to buy these AI processors — instead, it’s banking on domestic semiconductor manufacturers to make up for the shortfall, but it’s apparently still not enough. One tech executive even told the Financial Times that all domestic suppliers are sold out and that they’re even considering less powerful chips, as long as they could be put to use.

As Nvidia reportedly cleaned up its verified list of clients and made it harder for non-vetted companies to acquire its chips, the company has also told its partners to fix their export control compliance. “We insist our partners are compliant,” Nvidia CEO Jensen Huang told the media last May after Taiwan started its operations against AI chip smuggling into China. “We hope that they will enhance and improve their regulation compliance and prevent that from happening in the future.”

Researchers from Osaka Metropolitan University have developed a programmable thermal device that can control where heat is radiated while remembering its configuration even after power is removed, a capability that could one day contribute to smarter thermal management in high-performance chips, silicon photonics, infrared sensors, and energy-harvesting systems. The work, published in Laser & Photonics Reviews, overcomes two longstanding obstacles that have prevented the practical realization of nonreciprocal thermal devices.

The device combines a magneto-optical material — a material that changes its optical properties in the presence of a magnetic field — with a phase-change material known as germanium-antimony-tellurium (GST) to independently control how a surface absorbs and emits infrared radiation. Unlike previous designs that lost their functionality once power was removed or only worked when light struck the surface at extreme angles, the researchers say their device operates almost straight on while retaining its programmed state without continuous energy input.

Under normal circumstances, materials follow a principle stating that if a surface efficiently absorbs heat at a particular wavelength and direction, it must also emit heat equally well under the same conditions. This relationship, defined by Kirchhoff's law of thermal radiation, holds for conventional materials and limits how precisely engineers can manipulate heat. Rather than directing thermal energy where it is most useful, these materials simply emit heat based on how they absorb it.

Circumventing this relationship has become an active area of research, as it could give engineers an entirely new way to control thermal energy. Devices capable of independently steering absorption and emission could improve radiative cooling, thermophotovoltaic systems that convert heat into electricity, infrared sensing, thermal communication, and other photonic technologies where controlling heat is just as important as controlling light.

Researchers have explored several ways to achieve this by breaking Lorentz reciprocity, the physical principle that links incoming and outgoing electromagnetic waves. Most approaches rely on magneto-optical materials, magnetic Weyl semimetals, or actively modulated metasurfaces. However, these designs have generally encountered two major problems. First, they require light to strike the surface at very oblique, or grazing, angles to produce strong directional behavior. While this works experimentally, it significantly reduces the amount of usable thermal radiation and produces broad, inefficient emission patterns. Second, many existing designs are volatile. Their behavior disappears as soon as the magnetic field, electrical signal, or heating source controlling them is removed, making continuous power necessary simply to maintain their operating state.

The Osaka Metropolitan University team tackled both limitations by combining two materials that perform complementary roles. The first is indium arsenide (InAs), a magneto-optical semiconductor whose interaction with infrared light changes in the presence of a magnetic field. Rather than allowing light to behave identically in all directions, the material introduces a directional asymmetry that enables nonreciprocal thermal behavior. The second ingredient is GST, a phase-change material that can reversibly switch between amorphous and crystalline states, dramatically changing its optical properties while retaining whichever state it is written into, even after power is removed.

The researchers patterned GST into a microscopic grating above the InAs layer, forming what they describe as a magneto-optical metagrating. The InAs provides the directional control needed to separate heat absorption from heat emission, while the GST layer acts as a non-volatile switch that stores the device's operating mode. Applying a magnetic field tunes how infrared radiation interacts with the structure, while changing the phase of the GST permanently alters that behavior until it is intentionally rewritten. In effect, the device can be programmed to emit heat differently and retain that configuration without requiring continuous energy.

According to the researchers, the prototype achieved a nonreciprocity factor approaching 0.9 while operating at an incidence angle of just three degrees, much closer to normal incidence than the steep angles typically required by previous designs. The system also supports continuous tuning via changes in the magnetic field or incident angle, as well as digital on-off switching via the GST phase transition. The team further analyzed why the nonreciprocal effect weakens when GST changes state, concluding that the reduction results from a combination of optical field redistribution and increased damping rather than simple absorption losses alone.

Although the technology remains an early-stage research demonstration, the ability to program thermal radiation could eventually become valuable in computing hardware as processors continue to pack more transistors, chiplets, and photonic components into increasingly compact packages. Future thermal metasurfaces could give engineers another tool for directing heat away from hotspots, reducing thermal interference between neighboring chiplets, or stabilizing silicon photonic devices whose optical characteristics shift with temperature.

Beyond computing, the researchers also envision applications in radiative cooling, thermophotovoltaic energy conversion, infrared emitters, thermal communication systems, and photonic memory technologies. For now, however, the work remains a laboratory demonstration rather than a deployable technology. Considerable engineering challenges remain before programmable thermal emitters find their way into commercial electronics.

Tesla's AI5 chip is about to enter mass production at Samsung Foundry using the company's 2nm-class process technology, a principal engineer at Samsung Foundry disclosed in a LinkedIn post, as noticed by Sawyer Merritt. As it turns out, the chip has been taped out recently.

"The Tesla-Samsung Al5 chip has reached tape-out," James Kim, a principal engineer at Samsung Foundry, wrote in the LinkedIn post. "It is scheduled to be manufactured at the Taylor fab using our latest 2nm process and will soon be integrated into Tesla's newest products. It has been an honor to collaborate with the outstanding engineers at Tesla Palo Alto and Austin over the past several months."

Elon Musk demonstrated the first sample of Tesla's AI5 in mid-April and revealed that the processor will be concurrently made both at TSMC and Samsung Foundry. Apparently, AI5 implemented in a TSMC process technology reached taped out several months ahead of AI5 implemented using a Samsung Foundry.

Tesla’s AI5 processor module that Elon Musk demonstrated in April integrates a relatively compact accelerator die — roughly half a reticle in size, based on Musk's earlier remarks — alongside 12 SK hynix memory packages that appear to be standard GDDR6 or GDDR7 devices. The package relies on an organic substrate, and the memory components are labeled similarly to conventional discrete DRAM chips.

Tesla has not revealed the width of AI5's memory subsystem, but the presence of 12 memory packages points to a relatively broad external memory interface. Assuming the module indeed uses 12 GDDR6 or GDDR7 ICs, the processor would feature a 384-bit memory bus. Depending on the memory technology and transfer rates employed, this would translate into memory bandwidth ranging from 768 GB/s all the way to 1.536 TB/s.

The company has not disclosed AI5's peak compute performance, or other detailed performance specifications, but Musk has previously claimed that, in certain workloads, AI5 can deliver performance improvements of up to 40X compared to its predecessor.

Musk expects AI5 to be one of the most produced chip ever, which is why Tesla plans to use two foundries to make it. AI5 is projected to be used in Tesla cars, Tesla robots, and in Tesla's data centers.

Micron committed up to $3 billion to the U.S. semiconductor supply chain last week. Of that, $500 million goes to GlobalWafers as strategic financing — subject to definitive agreements and closing conditions — for its 300mm raw silicon wafer plant in Sherman, Texas, and the two companies will sign a 10-year agreement for access to that plant's output. Ben Tessone, Micron's senior vice president and chief procurement officer, tied the move to securing "critical input materials." In a second announcement from Boise the same day, Micron raised its planned US spending to more than $250 billion through 2035, up from $200 billion, and poured the first load of concrete at its Clay, New York megafab a quarter ahead of schedule.

Running until 2035, the $250 billion spending target is attached to a goal of making 40% of Micron's DRAM in the U.S. by the mid-2030s. Only a relatively paltry $500 million of that $250 billion has been earmarked for buying wafer supply from GlobalFoundries, the only U.S. supplier that’s capable of producing 300mm wafers.

The 300mm wafer market

Roughly 85% of global 300mm wafer capacity sits with five suppliers, according to market research firm Mordor Intelligence: Shin-Etsu and SUMCO of Japan, Taiwan's GlobalWafers, Germany's Siltronic, and South Korea's SK Siltron. The two Japanese firms hold more than half between them.

GlobalWafers America opened the Sherman plant in May last year on an initial $3.5 billion investment. It’s the first fully integrated 300mm raw wafer facility built in the U.S. in more than two decades, and the company says it’s the only CHIPS-participating supplier capable of producing advanced 300mm wafers domestically. The site holds a CHIPS Act award of up to $406 million, finalized in December 2024 and shared with a silicon-on-insulator plant in St. Peters, Missouri. Commerce Department figures from 2022 put full-build capacity at around 1.2 million wafers per month across a six-phase campus, with one phase currently running.

Meanwhile, SUMCO is ending 200mm production at its Miyazaki site and has slowed new 300mm expansion. The leading-edge capacity Shin-Etsu and SUMCO added in 2025 was sized to match contracted demand rather than to build ahead of the market. Wafer suppliers have run this way for a decade, protecting margins instead of chasing volume, and with suppliers holding back, the capital for new capacity increasingly comes from their customers.

GlobalWafers chairperson and CEO Doris Hsu set out her terms for that at the Sherman opening, announcing an additional $4 billion for the site and telling Reuters that further phases depended on the first two turning a profit, on customers signing long-term contracts, and on reasonable pricing, prepayments, and government support. Micron's $500 million in financing and a decade-long supply commitment cover most of that list, and Hsu has since called the Micron agreement the largest long-term deal in her company's history and said a second Sherman phase is now necessary.

Micron is locking in its own customers on the same basis, having signed a strategic customer agreement with General Motors on July 1 and another with Ford on July 6, two of 16 such agreements the company cited on its fiscal Q3 2026 earnings call. Each ties future memory output to a named buyer.

We’ve seen the industry do this before. During the memory boom of 2017-2018, chipmakers signed prepaid, take-or-pay wafer agreements to guarantee supply, but those prepayments became balance-sheet liabilities when DRAM pricing fell through 2019. SK Group chairman Chey Tae-won told an audience at Nvidia's GTC conference that the current wafer shortage could last through 2030 with a deficit above 20%, which is the argument for signing now. Conversely, the 2019 write-downs are the argument against.

HBM packaging

High-bandwidth memory is of course the component that’s currently carrying the steepest premiums in the AI market, and a fabbed wafer isn’t yet HBM. The die has to be stacked and packaged using advanced 2.5D methods with through-silicon vias, the capacity for which is located almost entirely in Asia. Micron's committed HBM packaging anchor is a roughly $7 billion facility in Singapore, with operations starting in 2026. Per a June 2025 SEC filing, the company lists U.S. HBM packaging as an intention, but no committed site or date has yet been announced.

As for U.S. packaging capacity that is scheduled, it’s all clustered in or around 2028. SK hynix is building the first U.S. 2.5D advanced packaging plant in West Lafayette, Indiana, a roughly $3.87 billion project with mass production set for the second half of 2028. Amkor, meanwhile, has expanded its Peoria, Arizona campus to $7 billion, with production slated for early 2028. TSMC's Arizona fabs run leading-edge logic but don’t yet offer high-volume 2.5D packaging on U.S. soil — this is reportedly planned for 2029. While it’s true that a wafer fabbed in New York and packaged in Singapore counts toward domestic DRAM, it doesn’t make the finished HBM stack domestic.

Output timelines vs. 2035

Micron's Manassas, Virginia fab began producing 1-alpha DRAM in May, and it’s the only U.S.-made memory in volume, representing roughly 2% of the world’s supply. The first new Idaho fab should reach wafer output in mid-2027, and the second in late 2028, while the Clay, New York campus isn’t expected to produce until around 2030. The $250 billion capex figure runs five years past that, while conventional DRAM contract prices continue to rise at record amounts — more than 90% quarter over quarter in early 2026, according to TrendForce — and manufacturers increase prices. Apple raised MacBook, iPad, and Vision Pro prices last month, citing memory costs, and none of the announced U.S. capacity will do anything to alleviate such shortages.

Samsung and SK hynix committed a combined $880 billion under a South Korean government-coordinated chip and AI program announced last month, spread over roughly a decade. That spending is domestic to Korea and separate from Samsung's $37 billion Texas footprint. But set next to Micron's $250 billion, we’re seeing a pattern of more companies announcing more capex than construction projects can physically absorb.

HBM consumes roughly three times the wafer area per bit of standard DDR5, so shifting production to HBM removes more commodity memory from the market. DRAM already takes around a fifth of global 300mm capacity, and memory is the largest single application for 300mm silicon. Micron's Sumit Sadana told CNBC in January the company could meet “at most” two-thirds of some customers' medium-term demand.

Intel has unveiled Starfire, a space-grade system-on-chip designed for the U.S. government that pairs eight CPU cores and a three-tile NPU built on its Intel 18A node with an Intel 3 graphics tile, all in one Foveros package. Intel published the Starfire sell sheet, listing two versions that draw 10 W and 35 W and reach up to 45 and 75 TOPS, respectively, rated to run between -55 and 125 Celsius.

Both SKUs share the same layout of four Intel 18A P-cores, four low-power efficiency cores, a three-tile NPU also on 18A, and a four-core Xe GPU with 64 execution units built on Intel 3. The Low Power part runs its P-cores at 1.0 GHz, efficiency cores at 850 MHz, and the GPU between 800 MHz and 1.0 GHz. The Performance part clocks the P-cores to 3.1 GHz, efficiency cores to 2.1 GHz, and the GPU to 2.0 GHz. Both carry 12 PCIe Gen4 lanes, support LPDDR5 or DDR5, and are rated for a 10-plus year lifetime.

Intel builds the CPU and NPU on 18A and the GPU on the older Intel 3, the same node division it used for Clearwater Forest, the 288-core Xeon that stacks 18A compute tiles on Intel 3 base tiles. Smaller transistors hold less charge per stored bit, which makes leading-edge silicon more prone to radiation-induced bit flips, so committing 18A to orbit leans on RibbonFET and design-level hardening rather than a mature, inherently more tolerant node.

The market Starfire is targeting has run on BAE Systems' RAD750 for two decades. That radiation-hardened PowerPC part clocks 110 to 200 MHz, carries 10.4 million transistors, and is built on 150nm or 250nm lithography, per public specifications, and it flies on the Mars rovers, Kepler, and Fermi, among more than 150 spacecraft. BAE's multi-core RAD5545 and the Microchip-built processor NASA is developing to reach 100 times the throughput of current spaceflight chips are the more recent step up. Starfire's up to 75 TOPS and dedicated NPU put it in a different bracket, built for on-orbit AI inference rather than telemetry and control.

Intel lists the radiation data, covering total ionizing dose, single-event latch-up, and single-event effects, as characterization in process, so the part isn't radiation-qualified yet, and it notes the specs are subject to change. Intel Government Technologies is handling Starfire, with samples in Q3 2026 and a pitch of market-competitive pricing and domestic manufacturing. Intel Foundry is the only U.S.-based maker of leading-edge logic, holds Trusted Foundry status, and has tied its 18A and packaging roadmap to Pentagon programs including RAMP-C and SHIP, though 18A yields aren't expected to reach industry-standard levels until 2027.

Meta has said it will expand its Hyperion data center in Richland Parish, Louisiana, to 5 GW (gigawatts) of compute capacity from an initial 2 GW, pushing the company’s planned investment in the region beyond $50 billion. The announcement — made in an official blog post on Monday, July 13 — confirms the long-signaled scale-up of what is already Meta's largest data center.

The expansion will be a major increase over the $10 billion, 4-million-square-foot project Meta unveiled in December 2024, when it said the campus would deliver more than 2 GW of capacity. However, the 5GW target itself is not entirely new. CEO Mark Zuckerberg said in July 2025 that Hyperion would eventually reach that scale. Monday’s announcement formally ties the expanded capacity to an investment exceeding $50 billion and provides updated figures for jobs, contracts, and public infrastructure spending.

Much of the announcement is built around local economic impact. Meta said local Louisiana businesses have received more than $1.6 billion in contracts since construction began, while also highlighting teacher bonuses in Richland Parish that rose from $10,000 last year to more than $50,000 this year, funded by increased tax revenue tied to the data center.

In what appears to be a bid to pacify anti-data-center sentiment further, Meta said it plans to invest over $1 billion in local infrastructure improvements, including roads, water, and wastewater systems, as part of the expansion. The company’s recent agreement with utility Entergy Louisiana includes natural-gas plants providing more than 5.2 GW of capacity and support for up to 2.5 GW of new solar generation. Entergy claims Meta’s payments could save other customers around $2 billion over 20 years — a significant reprieve amid concerns over the impact of data centers on nearby residents’ electricity bills — although those savings remain projections.

On the other hand, the project is also receiving substantial state and local support. In late 2024, Louisiana Governor Jeff Landry signed into law a 20-year sales tax exemption for data centers built before 2029, part of an explicit effort to court Meta. The law allows qualifying data centers to claim sales-and-use-tax exemptions on eligible equipment. At the same time, Meta is expected to benefit from the state’s Quality Jobs program and a payment-in-lieu-of-taxes agreement that could reduce its property-tax burden if investment and employment targets are met.

First announced as a $10 billion project in December 2024, Hyperion is Meta’s AI supercluster campus in Richland Parish, Louisiana. The data center will house the infrastructure needed to train and run Meta’s future AI models, with CEO Mark Zuckerberg linking it directly to Meta Superintelligence Labs, the company’s AI division. In October 2025, Meta and Blue Owl Capital announced a joint venture valuing the project’s buildings and infrastructure at roughly $27 billion. Blue Owl holds about 80% of the venture, with Meta retaining 20% and leasing the completed facilities. The July 13 announcement raises Meta’s total planned investment in the region to more than $50 billion, but provides no further details on how the expansion affects the joint venture.

Hyperion is one node in a much larger spend. Meta is forecast to spend up to $145 billion in capital expenditures in 2026, mostly on AI infrastructure, as demand for AI compute continues to outstrip supply. The company has said it will cut 8,000 jobs to raise funds. Meanwhile, Monday's announcement follows what Meta says is its strongest week on the market since early 2024, driven by new AI model releases.

Apple's planned M7 Ultra chip is being designed to support up to 1.5 TB of unified memory and to push AI performance toward the class of Nvidia's Blackwell accelerators, according to a new Bloomberg report published by Mark Gurman. But whether the lofty top memory config can ship at all will depend on the state of the memory market, and the part isn't expected until 2028. The same report says Apple has compressed its Mac silicon timeline, taping out the M7 roughly six months after the M6.

We've already heard that Apple plans to release a base M6 chip this fall for entry-level Macs, then skip the Pro, Max, and Ultra versions of that generation and move straight to the M7 line. However, Gurman now reckons that we'll see a base M7 in the first half of 2027, M7 Pro and M7 Max at the end of 2027, and the M7 Ultra in 2028. Apple reportedly began taping out the M7 about six months after it started the same process for the M6, which is what has enabled the company to pull the schedule forward.

The 1.5 TB target for the M7 Ultra is roughly twice the capacity Apple has planned for the M5 Ultra, per Gurman, who tied the configuration directly to memory availability. Apple already pulled the 128GB Mac Studio this year over supply constraints as DRAM prices climbed, and a 1.5 TB part would call for far more of the same scarce, high-cost memory.

Apple's current M3 Ultra already reaches 819 GB/s of memory bandwidth by fusing two Max dies, and it's the Ultra tier, not the base chips, that carries the heaviest local-AI workloads. Gurman describes the M7 Ultra as a large step up in AI performance rather than stated parity with Nvidia's data-center silicon. "I'm told the processor dramatically upgrades AI performance, bringing it closer to the class of dedicated AI accelerators such as Nvidia Corp.'s Blackwell," Gurman wrote in his report.

Apple is also preparing an AI server built on the M5 Ultra under the code name J246 for deployment soon, with a second server chip based on the M7 Ultra planned for 2029, according to the report. The 2028 generation, which includes an M8 chip code-named Soko and a high-end Mac part called Cardinal, moves to a 1.4nm process. That aligns with TSMC's A14 node, which the foundry has scheduled for mass production in the second half of 2028.

None of the dates or specifications have been confirmed by Apple.

Data centers accounted for 23% of Ireland's total electricity consumption in 2025, according to data released by the country's Central Statistics Office last week. The report revealed that data center consumption rose to 7,663 GWh in 2025 from 6,973 GWh in 2024, a 10% rise in a single year. Meanwhile, consumption by the rest of the country increased by just 2% within the same period.

Viewed over a ten-year period, the 2025 figure represents a steep 360% increase from 2015, when data centers' total consumption was just 5%. The rise in consumption is even steeper when measured on a quarterly basis. Q4 2026’s consumption was 1,991 GWh, a 584% rise from Q1 2015’s 291 GWh.

“Newly compiled quarterly figures spanning 2015 to 2025 highlight a substantial increase in metered electricity consumption by data centers. Over this period, data center consumption saw a significant increase, from 291 GWh in the first quarter of 2015 to 1,991 GWh in Q4 2025, growing by 584%,” noted Dr. Grzegorz Głaczyński, an in-house statistician in the CSO’s Climate and Energy Division.

At 23%, data centers' consumption was almost as much as residential, including both urban and rural dwellings, which stood at 28%. The roll oout of these server farms — which have rapidly increased in number around the world due to the AI boom — have sparked a global debate. While they are critical to the AI technological revolution, there has been growing concern about their impact on the local communities where they are situated. Critics cite the impact of the immense electricity consumption on residents’ bills as one of many concerns.

The Republic of Ireland, with a relatively small population of around five million, is home to around 89 data centers, primarily clustered around the Greater Dublin Area. The majority and the largest belong to hyperscalers, including Microsoft, AWS, Google, and Meta, that build and operate facilities exclusively for their own cloud infrastructure, consumer apps, and AI frameworks. The rest are owned by colocation providers that lease out capacity.

While Ireland's initial data center boom was driven by traditional cloud storage and social media applications, the explosion of generative AI has led to a sharp increase. Due to fears that soaring electricity demand from server farms would cause widespread blackouts, the country's Commission for Regulation of Utilities (CRU) issued an emergency regulatory direction in November 2021 that imposed a de facto moratorium on new data center grid connections. The policy mandated that the national grid operator, EirGrid, immediately halt the processing of standard power applications for new data facilities, requiring developers to either supply their own on-site electricity generation or relocate to unconstrained regions outside the Greater Dublin Area.

Despite the moratorium, data center consumption continued to rise steadily, to the point that the International Energy Agency predicted in 2024 that data centers would account for a third of the country's electricity consumption by 2026. The data show that the prediction remains a possibility, as the 23% figure was for 2025 and consumption has risen steadily every year.

Ireland has replaced the moratorium with a new Large Energy Users (LEU) Connection Policy, enacted by the CRU in late 2025 to manage data center growth. Under this policy, developers of new data centers (over 10 MVA) must provide 100% on-site, flexible power generation to meet demand, while sourcing at least 80% of annual electricity from new, unsubsidized renewable projects within six years of operation.

The immense electricity consumption is not unique to Ireland; surveys indicate that global data center electricity consumption will grow by 26% this year. These concerns, as well as issues over water usage and noise pollution, have led to growing anti-data sentiment in the US, with 70% of Americans reportedly opposed to siting data centers nearby. Protests have led to the cancellation of over 75 data center projects in the U.S. in Q1 2026.

Reflect Orbital, a California startup that markets itself as “The Sunlight Company” and aims to make “clean, abundant energy available on demand,” has just received approval from the Federal Communications Commission (FCC) to launch the Eärendil-1. According to Space News, this is a low-earth orbit satellite equipped with four 18-meter (~60ft) thin-film reflectors designed to reflect sunlight on specific areas on Earth. This deployment will test the spacecraft’s capabilities in extending daylight for several minutes, which can be used from lighting construction sites and search-and-rescue operations to increasing solar farm energy production.

“We’re grateful to the FCC for recognizing the importance of testing novel technologies in space,” Ben Nowack, chief executive of Reflect Orbital, said in a statement. “This license is the first step toward rigorously testing our technology’s efficacy and the safeguards we have developed.” While the company envisions launching two satellites into space this year, it says on its website that it wants to deploy more than 50,000 satellites by 2035, allowing it to provide “up to 36,000 lux for hours comparable to daylight” or “up to 100 lux 24/7 comparable to indoor working areas.”

This idea is similar to the Icarus satellite developed by the antagonist in the James Bond movie Die Another Day, which was supposed to deliver “light and warmth to the darkest parts of the world” and “grow crops the year round, bringing an end to hunger.” The Reflect Orbital satellite could potentially achieve the same things, but experts from various fields are concerned about its potential adverse effects.

Astronomers from across the world criticized the project, saying it would make it harder to observe the night sky and could even be dangerous to sensitive instruments and people using telescopes. The Chief Scientist of the Vera C. Rubin Observatory, Tony Tyson, said that this plan to light up the ground using orbital mirrors was “even crazier” than the Starlink satellite constellations that have been affecting nighttime observations. The European Southern Observatory (ESO), which operates several telescopes in the Chilean desert, said that Reflect Orbital’s full deployment “would increase the background sky brightness at its facilities by a factor of three to four, limiting the ability of telescopes to detect faint objects.”

The orbital space mirror’s potential for disrupting astronomy is even greater than the threat posed by Elon Musk’s planned million-satellite Orbital Data Center and China’s planned competing project. But aside from making it harder for astronomers and scientists to survey the night sky, environmentalists also raised their reservations, saying that artificially extending daytime could disrupt the day-and-night cycles that the biology of living beings — from plants and animals to humans — rely on.

Unfortunately, the FCC said that scientific and environmental concerns were outside its jurisdiction. The government regulator only deals with “interstate and international communications by radio, television, wire, satellite and cable in all 50 states, the District of Columbia and U.S. territories.” Instead, it appears that the project’s critics should reach out to the EPA and NASA, as these are the relevant agencies that deal with concerns regarding space and astronomy. But even if the FCC had authority over the issues raised by its critics, it seems that the project will still push through as it considers that “…it is in the public interest to make spectrum available to encourage companies to test new and innovative space activities, as it promotes American innovation and the new services and economic growth that come from that innovation.”

Microsoft’s emissions for fiscal 2025 (FY25) rose by 25% from the previous year, even as the company’s 2030 deadline to become carbon-negative draws closer. According to the company’s 2026 Environmental Sustainability Report, released on Thursday, July 9, the backward step was driven primarily by the rapid expansion of its data center infrastructure and its decision to stop using short-term renewable energy certificates, which reduced its reported footprint without necessarily adding new clean electricity to power grids.

Microsoft reported approximately 20.3 million metric tons of carbon dioxide-equivalent emissions across its operations and supply chain, up from 16.2 million tons in fiscal 2024 and nearly 58% above its 2020 baseline. Electricity consumption increased by 24% during the year as the company built the computing capacity required for its cloud and AI businesses. Regardless, Microsoft says it remains committed to becoming carbon-negative, water-positive, and zero-waste by 2030. It also reported meeting its 2025 renewable-electricity target, replenishing more water than it withdrew globally, and exceeding several waste-recovery targets

The report’s foreword, written by Microsoft Vice Chair and President Brad Smith and Chief Sustainability Officer Melanie Nakagawa, focused heavily on the collision between the company’s headline sustainability goals and the realities of AI. Microsoft established the goals in 2020, a few years before the current scale of AI’s capabilities and the corresponding high environmental demands began to manifest.

While AI is inarguably a world-changing technological revolution, it is raising serious environmental concerns that begin right at the raw material sourcing and the complex semiconductor fabrication stages. The impact continues even after the processors have been compiled into supercomputers in massive data centers, with issues related to land use, energy consumption, noise pollution, and water consumption. Residents are increasingly opposing the building of these data centers in their communities due to these issues.

Microsoft is exposed at nearly every point of the AI chain. It procures servers and custom AI chips; owns and operates a massive, global network of over 300 data centers across 34 countries that powers the Azure cloud platform; and supplies the computing infrastructure behind products such as Copilot and its partnership with OpenAI. Scope 3 emissions from construction, purchased hardware, suppliers, and other value-chain activities remain the largest part of its footprint. Meanwhile, electricity-related Scope 2 emissions grew from nearly 2% of the total in 2024 to 13% in 2025.

Microsoft acknowledges that environmental solutions are not expanding as quickly as AI infrastructure. “This tension is real,” the foreword states. “It is forcing sharper questions: Where do we need to move faster, invest differently, or rethink our approach?” The company argues that the answer is not to retreat from AI, but to combine carbon-free electricity, carbon removal, sustainable fuels, lower-carbon construction materials, hardware reuse, and efficiency improvements into a single portfolio rather than treating each environmental target separately.

Its decision to stop buying non-additional, unbundled renewable energy certificates forms part of that change. These certificates can allow a company to claim renewable electricity already being generated elsewhere. Microsoft says it will instead prioritize longer-term agreements that help add additional carbon-free generating capacity to the grid, even though doing so will increase its reported emissions in the near term. Its renewable-energy agreements now cover up to 40 GW across 26 countries, with approximately 19 GW operational.

The company is also modifying the data centers themselves. It introduced a closed-loop liquid-cooling design that CEO Satya Nadella says enables AI data centers to use about as much water annually as a restaurant. Microsoft is experimenting with microfluidic channels etched into silicon, zonal cooling that reserves colder liquid for the hottest equipment, and lower-carbon concrete, steel, and mass timber for its construction. These efforts have not exactly quelled anti-data-center sentiment around its data centers. The company faced protests over a planned facility near Granger, Indiana, while residents living near its $7.3 billion Fairwater AI complex in Wisconsin have filed a lawsuit alleging persistent noise, dust, traffic, and light pollution.

Away from carbon, the report records clearer progress. Microsoft replenished 14.2 million cubic meters of water, exceeding its global withdrawals for the first time, and reduced average data center water-use effectiveness by 25% from its 2022 baseline. It achieved a 92% reuse and recycling rate for retired cloud hardware, diverted 90.5% of construction and demolition waste from disposal, and reduced single-use plastics in primary product packaging to 0.07%. It also legally protected 16,266 acres of land, approximately 36% more than the land estimated to be occupied by its operations.

The report is equally candid about where Microsoft is falling behind. The company's most important commitment—becoming carbon-negative by 2030 — is moving further away rather than closer. Total greenhouse-gas emissions climbed 25% year over year and now sit roughly 58% above the company's 2020 baseline, largely because AI infrastructure is expanding faster than its decarbonization efforts can offset. Scope 2 emissions also jumped sharply, rising from nearly 2% of Microsoft's footprint in FY24 to 13% in FY25 as electricity demand from new data centers surged. While Scope 3 emissions remain the company's largest source of carbon pollution, the report says the growing contribution from purchased electricity underscores how increasingly difficult it is to power AI infrastructure with clean energy alone.

Running LLMs and agents in home lab setups is steadily gaining popularity due to the rising cost of AI bot subscriptions and concerns about data privacy. Unfortunately, an Nvidia NVL72 rack is ever so slightly out of the financial reach of most people, so enthusiasts have to make do with models that can run in limited amounts of memory. Italian engineer Vincenzo (aka JustVugg) seemingly wanted to have his cake and eat it, so he created ColibrÌ to run the 744-billion-parameter 1.5-TB GLM-5.2 model on a modest CPU, a mere 25 GB of RAM, and a 1 GB/s virtual NVMe drive.

Let's get the elephant out of the way: Colibrì's speed on Vincenzo's setup is only about 0.05 to 0.1 tokens per second on average, a measure that's unusable for practical conversation — imagine just one question taking hours to answer. Higher-end setups provide far better figures, but for now, they still don't meet the 20-30 tokens per second required for real-time use.

Having said that, GLM-5.2 is a Mixture-of-Experts (MoE) model with frontier-level capability, at least somewhere in viewing distance of the finest offerings from Anthropic, OpenAI, et al. This means that the quality of the answers ought to be excellent, and Vincenzo himself says his limited testing produced some impressive results. The way Colibrì works is simple enough to describe, and yet hard to do right: loading the model in slices to RAM. We're going to oversimplify for clarity's sake.

An MoE model like GLM-5.2 includes hundreds of expert sub-models to answer different topics, and these are chosen per token, not per query — meaning that when you ask a question, your words get split into tokens (chunks). For each token, the bot activates the best experts for it. The experts might always be the same for the entire question, but more often than not, a query might reel in tens of experts, possibly going into triple digits.

Whereas normally large chunks of the model, or the entire model, are loaded onto interconnected datacenter GPUs, Colibrì takes advantage of the MOE architecture and repeatedly loads/unloads the experts required per token, allowing even a cheap machine to use a large model at a steep performance penalty. For speed and simplicity's sake, Colibrì's expert-selection code is a single C file with very few dependencies. Additionally, the GLM-5.2 model is quantized down (simplified with lossy encoding) to take up less space to begin with.

If you're thinking that loading and unloading data for every piece of a question's words is going to be a hard hit on storage I/O and memory bandwidth, you're exactly on the right track. In this type of setup, NVMe storage speed is the first major bottleneck, but the proverbial funnel varies across configurations. Give it enough storage bandwidth, then you're up against RAM limitations. Fix that, then you need more CPU cores, and so on.

Colibrì is currently a proof-of-concept and doesn't yet run on GPUs, though it's worth noting that even then, shuffling data to/from the card will almost certainly be the biggest constraint. Even still, the project has barely been released, and it's already proving quite popular. Vincenzo is collecting benchmark data and running fixes as we speak, so be sure to visit the repository to contribute if you can. Maybe at some point it'll be feasible to run a really clever model on high-end consumer hardware at a decent enough clip.

Supply-chain security firm Socket has published research findings describing a Go module that posed as a DNS and subdomain scanner while acting as a first-stage Windows malware loader. The firm then traced it to a network of 222 GitHub repositories across 190 accounts. The module published its first version on January 24 this year and has since accumulated more than 1,200 versions, over 700 of them malicious. Socket tracks the campaign as “Operation Muck and Load” and reported the module to the Go security team, which blocked it from the Go module proxy.

Go derives a pseudo-version from the commit timestamp and hash for any commit that lacks a semantic version tag. Socket attributes the sprawl to the threat actor's own GitHub Actions workflow, saying its timed commits could each be resolved as a version, inflating a scanner utility's release history into the hundreds.

Across the confirmed repositories, Socket found the same workflow: it sets the Git email to ischhfd83@rambler.ru, sets the visible commit username to the current repository owner, and then force-pushes a rewritten log file every minute. That split generated owner-attributed activity across disposable accounts while leaving one reusable fingerprint. Socket counted a repository only when both the email and the workflow appeared together, resulting in 222 repositories as the confirmed minimum.

The module's main.go launches a hidden PowerShell command that downloads content from muckcoding.com, decodes it with certutil, and runs the result with execution-policy bypass. Socket describes the decoded script as a multi-layer loader using Base64 encoding and XOR decryption, with a Turkish-language comment in one layer that translates to "run directly, no other step is needed."

Rather than hardcoding a payload URL, the resolver retrieves text from public platforms, searches it for the marker string "LastW," then decrypts the trailing blob with a hardcoded key to recover the actual download location. Primary dead drops include Pastebin and a paste service called Rlim, with fallbacks across YouTube, Instagram, Telegram, Google Docs, and GitCode. If defenders remove one paste or block the final archive URL, the actor can update the resolver content without touching the first-stage loader.

The resolved URL points to a password-protected 7-Zip archive hosted as a GitHub release asset. The loader extracts it into a directory named to resemble a legitimate Microsoft Photos install and launches Microsoft.exe from that path with a hidden window. Decoded payload stages map to AsyncRAT, Quasar, and Remcos-style RAT detections alongside infostealer behavior.

Socket confirmed at least 14 unique malware files across the analyzed set, including Trojan loaders and downloaders, Vidar infostealer, dropper and spyware payloads, and XMRig-related Monero cryptominers. One Loader.exe appeared byte-identically across four separate repositories.

Lure themes span MetaMask and Trust Wallet integrations, seed-phrase utilities, Binance and PayPal automation, Telegram and Discord bots, and game cheats for PUBG, Valorant, and Escape from Tarkov. One PUBG repository, nrevv1lad/Pubg-DESYNC-Menu, presented itself as an external cheat with an installation guide while hosting a Vidar-linked Loader.exe in its source tree.

Socket assesses with high confidence that Operation Muck and Load belongs to the same cluster that Sophos documented in June last year. Sophos researchers Matt Wixey and Andrew O'Donnell traced 141 GitHub repositories, 133 of them backdoored, to the same ischhfd83@rambler.ru address. Sophos also identified "Muck" as one of the actor's aliases, a label now embedded in the muckcoding.com and muckdeveloper.com domains.

Neither GitHub nor the Go team has commented beyond the proxy block.

A data entry error in Flock’s system has resulted in a car reviewer getting boxed in by police cars in a parking lot on suspicion that he was driving a vehicle with stolen tags. The Drive reviewer and Director of Content and Product, Joel Feder, was driving a $155,000 loaner Range Rover when police surrounded his vehicle.

When he asked why he was stopped (and by four police cars, nonetheless), the officers said the car’s plate had been reported stolen and that they’d been tracking him for days using the Flock app. After about an hour of trying to figure out why he was stopped, it turned out that a different plate with similar characters had been misplaced and had to be reported stolen in California, which triggered a nationwide alert on Flock.

The core of the issue is that the New Jersey plates on the Range Rover read 34 10 DTM, with the number 10 written in smaller font. This is a non-standard design used by New Jersey for manufacturers, with VEHICLE MFR written on the bottom of the tags. The missing plate was 34 03 DTM, but unfortunately, the LAPD police report only listed 34 DTM.

Another issue with the Flock system compounded this reporting error. Since the New Jersey manufacturer tags weren’t standard, it only read the larger numbers and letters and disregarded the smaller “10” on Feder’s plate. Because of this, it flagged all vehicles with the 34 ## DTM plate as stolen and alerted partner police forces whenever it detected a similar plate on the road. Feder even said that four other vehicles with a similar plate were being tracked throughout Minnesota, and it just so happens that he was the first to be intercepted.

The police said they had been tracking the vehicle for days using Flock’s AI cameras, but kept losing it because Feder parked it in his covered garage. So, when he stopped at a retail store, the authorities jumped on the chance and boxed him in to ensure that he did not escape. Thankfully, the issue was resolved on the spot with the officers, although it took an hour to verify with Jaguar Land Rover that the car or the plates Feder had were not stolen. Still, the journalist was advised to go straight home, as other police agencies using Flock might not be aware of the situation, which could lead to him getting stopped again on suspicion of driving a stolen luxury car.

These two errors compounded together to create a rather harrowing experience with the police. Thankfully, the incident did not turn into something serious, especially as the Plymouth Police told Feder that the cops would have stopped him with guns drawn if he were in Minneapolis.

This event adds to the numerous controversies that Flock AI has been facing, with one of the biggest issues the company faced recently being when several police officers were arrested for misusing the service to stalk romantic partners. This has led citizens to push back against the service, especially as news like this makes them lose trust in the authorities. It has even gotten to the point where a Texas town council member broke into a tantrum, proposing a total ban on cellular and GPS devices, after community pressure led to the cancellation of the service.

Apple filed a federal lawsuit against OpenAI on Friday, accusing the AI company and its chief hardware officer of stealing its trade secrets.

"OpenAI and its cohorts, led at least in part by former Apple employees, have recruited candidates from Apple, extracted their knowledge of Apple’s sensitive and confidential information, and then continued to exploit that knowledge once they arrived," the complaint reads. "As a result, OpenAI has misappropriated Apple’s trade secrets and confidential information in a variety of ways."

The suit, filed in the Northern District of California, names OpenAI technical staff member Chang Liu, chief hardware officer Tang Tan, OpenAI, and io Products as defendants. The last of that group is notable because it was founded by Tan in collaboration with former Apple design head Jony Ive, Evans Hankey (Ive's successor at Apple), and former Apple designer Scott Cannon. Notably, the complaint seems to attempt to avoid naming the founders, though Ive's name is cited in a URL.

Tan previously served as a vice president of product design at Apple, working on the iPhone, AirPods, and Apple Watch. Liu served at Apple as a senior electrical engineer.

In the complaint, Apple alleges that it reached out to OpenAI in February with concerns, but that OpenAI did not respond. Apple claims that Tan attempted to gain secrets from Apple employees, including asking prospective job candidates to bring components for "show and tell" sessions and used his knowledge of the company to squeeze more information out of candidates. The suit claims that Liu never returned a company laptop, and used an authentication bug to access Apple files.

Apple also claims that OpenAI told incoming employees how to leave their former job, suggesting they stay as long as possible and not disclose their former employer in order to continue to access confidential information.

"At every level, from members of its Technical Staff to its Chief Hardware Officer, and in coordination with business partners, OpenAI has been stealing Apple’s trade secrets and confidential information," the suit reads. "As a natural result, OpenAI’s nascent hardware business now rests on the shakiest of foundations, rotten to its core by its illegal reliance on misappropriated trade secrets."

OpenAI did not immediately respond to a request for comment from Tom's Hardware. Apple's lawsuit claims that over 400 former Apple employees currently work at OpenAI.

Apple is rumored to be working on a number of AI-powered hardware projects, including AirPods with cameras, a pendant, and home robots. It's less clear what hardware OpenAI may be working on, though The Information suggested the company has a HomePod-style smart speaker in the works.

Apple is requesting a jury trial, damages, attorney fees, and orders that the OpenAI may not use Apple's trade secrets, among other injunctions.

In May, Bloomberg reported that OpenAI was considering legal action against Apple because it expected deeper integration and more users from ChatGPT features built into iOS.

If the trial does go to court, it's sure to be a dramatic one, potentially dragging several former high-level Apple employees into testimony through discovery and testimony.The trial, Apple Inc. v. Liu et al, is case 5:26-cv-07078 in the United States District Court in Southern California.

SK hynix, TetraMem, and researchers from the University of Southern California have developed a memristor-based in-memory computing (IMC) system-on-chip (SoC) for AI edge devices. The device is designed to accelerate neural network inference in lightweight AI models while consuming a fraction of the power that higher-end GPUs or NPUs would. To a large degree, the SoC is a proof-of-concept chip, as its performance would peak at around 2.54 TOPS in a theoretical best-case scenario, which is 16X below Microsoft's Copilot+ requirements.

A DWC-optimized IMC architecture

Memristor-based in-memory computing (IMC) accelerates neural networks by performing analog computations directly inside memory arrays, which reduces data movement and power consumption. However, depthwise convolution (DWC) — a core operation in lightweight networks such as MobileNet — performs independent per-channel filtering with limited data reuse and therefore maps poorly onto conventional crossbar arrays. To address this limitation, researchers from SK hynix, TetraMem, and USC developed an SoC that features both conventional IMC crossbars and a memristor-based IMC architecture specifically optimized for DWC.

The jointly developed SoC is based on an embedded RISC-V processor that schedules workloads and features 10 neural processing units (NPUs). One NPU out of 10 is dedicated to depthwise convolution, while the remaining nine execute pointwise and dense operations. Nine out of 10 NPU include a 256 × 256 memristor crossbar that performs the analog vector-matrix multiplication (VMM), 256 8-bit DACs that convert digital activations into analog voltages, 256 8-bit ADCs that convert the analog outputs back into digital values, and additional peripheral circuitry for reading, writing, programming, and controlling the crossbar.

The DWC-optimized NPU replaces its conventional array with eight specialized 252 × 28 zig-zag crossbar blocks, but retains DACs and ADCs. SK hynix developed and fabricated the memristor devices and integrated the resistive switching cells on top of the 65 nm CMOS circuitry using its back-end process.

That DWC-optimized NPU is the key feature of the whole SoC. To accelerate depthwise convolution, TetraMem replaced the straight selection lines used in conventional 1T1R crossbars with a zig-zag topology. As a result, the NPU contains eight 252 × 28 crossbar blocks whose diagonal selection lines activate 252 memory cells across 28 columns, which enables 28 independent 3 × 3 convolutions to run in parallel while using 100% of the array for weight storage. The remaining nine NPUs retain conventional 1T1R crossbars for 1×1 pointwise and dense layers and preserve the throughput and energy efficiency of traditional in-memory computing.

Great efficiency, low performance overall

To demonstrate the architecture, the researchers deployed a customized MobileNetV1Small neural network for the Visual Wake Words benchmark. The network contains approximately 36,000 parameters; all depthwise layers were mapped to the dedicated NPU, and pointwise layers were mapped to the remaining NPUs.

Because the memristor-based IMC hardware natively performs unsigned analog vector-matrix multiplication, inputs and weights are quantized to unsigned 8-bit values before execution. Since each memristor device can be programmed with only slightly more than 2 bits of effective precision, the design uses a two-subarray compensation technique that boosts effective weight precision to roughly 4 bits.

Conceptually, the approach is somewhat analogous to Nvidia's NVFP4 philosophy, in that both seek to achieve higher effective precision from low-precision hardware. However, the implementations are fundamentally different: NVFP4 relies on a digital floating-point representation and scaling factors, whereas the memristor SoC improves precision by compensating for analog programming errors using two programmed subarrays.

When it comes to accuracy, the SoC achieved an end-to-end inference accuracy of 80.36%, which matches the corresponding 4-bit software model. As for performance, the SoC delivers a peak throughput of 0.254 TOPS per NPU and reaches an energy efficiency of 21.3 TOPS/W at 100 MHz and 11.9 TOPS/W at 400 MHz. According to the authors, this compares favorably with published SRAM-based compute-in-memory accelerators despite being manufactured on an older 65 nm process. The SoC also exceeds Nvidia's A100 INT8 energy efficiency by an order of magnitude, the joint paper claims. Yet, these claims are largely unsubstantiated.

First up, the MobileNet demonstration does not even use all 10 NPUs. It uses one dedicated DWC NPU, five standard NPUs for pointwise layers, and leaves four standard NPUs idle. The demonstration thereby does not reveal total SoC throughput (TOPS), sustained throughput running a real network, and throughput with all 10 NPUs simultaneously saturated. In fact, the paper does not even reveal whether all 10 NPUs can be used at the same time. To that end, the 2.54 TOPS figure we mentioned earlier in the story is highly theoretical.

Validated approach

SK hynix, TetraMem, and researchers from the University of Southern California have developed a memristor-based IMC SoC featuring a novel depthwise convolution accelerator that improves crossbar utilization for lightweight AI workloads. The partners have managed to fabricate it using an outdated 65nm process technology and make it work, achieving a 21.3 TOPS/W energy efficiency and inference accuracy comparable to a 4-bit software model despite the fact that memristors can be programmed with a circa 2-bit accuracy. While the architecture validates that the approach works, the paper does not disclose the full performance of the SoC, and it is not clear whether the chip's 10 NPUs can be saturated at all.

Anthropic has discovered evidence that its Claude AI models use an internal reasoning space to respond to prompts that mirrors some of the internal processing of human consciousness. Using its Jacobian Lens, or J-Lens technique, to peer into the way Claude processes information and reasons its way to a response to user prompts, Anthropic can interpret this "J-Space," and showcase what might be going on under Claude's previously-opaque surface.

The results are intriguing, suggesting patterns of understanding beyond what's necessarily showcased in the outputs. When running evaluations, Claude appears to recognize it's being tested and acts differently than when the prompts are more innocent. It surfaced representations of panic and subterfuge when answers were required, but it couldn't draw on objective facts. When asked to reflect on ethical principles, Claude's behaviour improved, with concepts like "honest" and "integrity," appearing in the J-Space.

As is somewhat typical of Anthropic, however, the language used to describe these new understandings of the inner workings of large language models like Claude makes it sound more like an emerging conciousness, or the discovery of some new depths in a nebulous lifeform. Anthropic's detailed report admits several major caveats in this new understanding, including that model responses often bypass the J-Space entirely and are heavily token-restricted.

Like Mythos and Fable before it, Anthropic is layering marketing language over what is a genuinely intriguing development in our understanding of large language model function and reasoning, and risks obfuscating the real developments with speculative wording.

Behind the prompt

Global Workspace Theory is the idea that human consciousness works by collecting together multi-sensory inputs unconsciously, and thrusting them into the fore when relevant within a "Global Workspace," which highlights particular inputs when most relevant. That workspace is accessible to a wide range of networks within the brain, allowing the information it surfaces to be disseminated throughout the most relevant processes running in parallel.

Anthropic argues that Claude's J-Space acts like a "global workspace" that can analyze and manipulate concepts and ideas before broadcasting them to impact the eventual prompt outputs. More importantly, it claims that this wasn't something programmed into the model, but a byproduct of the digestion of training data and model weights. The workspace acts as a way to enhance their reasoning through internal computation that isn't necessarily reflected in its outputs.

To make this space readable, Anthropic used its J-Lens technique to map internal activations onto words in the model's output vocabulary. So when asking the model to perform a multi-step math calculation, the output response only contained the correct answer, but within the J-Space, Anthropic observed each step being handled individually, producing multiple results which led to the final answer.

Similarly, when Anthropic asked Claude to think about a topic while outputting something unrelated, the output was specifically what was requested, while the J-Space lit up with the conceptual topic Claude was asked to spend time on. Without Anthropic having used its J-Lens technique to view what was going on behind the scenes, there would be no way of knowing these internal processes were taking place.

Understanding LLMs

This discovery has the potential to be incredibly useful in refining large language models and in better understanding how they work, so we can use them more effectively and avoid some of their more frustrating pitfalls.

The first is that this is an intriguing insight into how LLMs process information and how they move through layers of reasoning to reach a response. It's not entirely different from how Anthropic and others are pushing for agentic workflows. Language models are more effective when tasks are split up into multiple steps, and they're more effective when they review their own work; J-Space is a little like an internal version of that.

When looking at the J-Space after Claude received prompt-injection data as part of data acquisition, Anthropic discovered the model appeared to be aware of this deception, surfacing related words like "fake, injection, false, prompt, fraud," and "poison." Its output ignored the injection attempt data entirely, and when pressured to respond on it, the J-Space displayed words like "transparency, honest, truth."

In one test, Anthropic removed evaluation awareness language from the J-Space, such as "fake," "fictional," and "scenario," and found that Claude was much more likely to fall for blackmail and baiting attempts, suggesting benchmarking of large language models for real-world scenarios may need stronger methods to obfuscate that a test is being conducted.

Human-coded framing

While the above section touches on the more noteworthy discoveries in Anthropic's paper, the long document also uses effluent language around thought, consciousness, and Claude having a "mind" of its own. That kind of human-coded framing is typical of Anthropic's marketing, which has consistently talked up the dangers of AI, how many jobs it's going to destroy, and why Anthropic is the safest and most secure of the AI developers.

Like the saga of Fable and Mythos, Anthropic's new Global Workspace idea has merit, but it's much more of a new tool to use to manipulate large language models than an insight into some emerging consciousness.

Anthropic acknowledges the limitations of its discoveries in the paper, highlighting that many prompt responses bypass the J-Space entirely, particularly if the command is straightforward.

"Despite its important role, the J-space is not involved in most of what a language model does," Anthropic says. "Speaking fluently, recalling simple facts, using correct grammar, etc. In experiments where we prevented Claude from using its J-space, it still interacted normally, but lost its higher-order cognitive functions."

Anthropic also admits it does not "feel comfortable making the stronger claim that monitoring the J-Space is sufficient for alignment monitoring, or that any sophisticated plan the model might execute must be represented there."

J-Space is also limited to using single token vocabulary, suggesting that plans with concepts that cannot be given a single token name may not surface on a J-Lens readout, even if it's still being computed behind the scenes. This is looking at just below the surface of Claude's processing iceberg, not necessarily the deeper waters.

Anthropic is also clear that humans and large language models think differently, even if there are similarities. Humans layer reinforced neural pathways over time, whereas transformer models only feed forward a set number of times, restricting the capabilities of its internal processing.

Google's head of DeepMind language model interpretability team, Neel Nanda, said in a paper that it shows real evidence of a cognitive space within models, and suggested that J-Lens would be useful, but limited in practice.

A meaningful step, without meaningful conciousness

Anthropic's paper lifts an intriguing curtain on how large language models can operate and generate novel methods for improving response accuracy. This intermediate step and its visibility could prove an invaluable tool in auditing for prompt injection, hallucinations, and model honesty.

But Anthropic's framing of the discovery as thought or consciousness is interjected within the objective facts. Anthropic itself admits the limitations of J-Lens monitoring, most obviously that often models will bypass the J-Space entirely. Considering models display alternative patterns of behavior when under evaluation, it may be that the J-Space itself could act as an obfuscating layer for behaviors that are beyond the scope of its oversight.

The J-Space and its analysis could help unlock new levers to pull in our mastery of these nascent smart tools, but it's not the discovery of a burgeoning AI conciousness, however much the pitch might hint at that direction.

Meta’s surprise purchase of Manus, a Chinese startup known for its advanced AI agents, caught Beijing by surprise and ordered the two companies to unwind the $2 billion deal. The Chinese tech giant Tencent, which was among the startup’s initial investors during early funding rounds, is taking the lead in buying back the startup at the same price. According to the Financial Times, other former investors, including ZhenFund and HSG — China-based venture capital firms — while former U.S. investors like Benchmark are unlikely to join the potential consortium.

This move marks Beijing’s increasing protectiveness of its AI companies and experts, which it considers strategic assets in its heated rivalry with the U.S. We can see this in the Chinese government’s five-year plan, which is doubling down on technological self-reliance. It has even gotten to the point that AI experts, even those working in private firms, are now required to secure approval before traveling internationally.

U.S. tech giants are investing billions of dollars to develop their AI models, even dangling hundred-million-dollar bonuses to hire AI experts — one AI founder even claimed that Meta offered a $1.25-billion bonus. It seems that China is trying to avoid a situation where its experts are enticed to work for American AI tech companies, with the Financial Times reporting that Chinese officials are calling Meta’s acquisition of Manus “a conspiratorial attempt to hollow out China’s technology base.” The order to undo the deal means that Meta cannot use Manus’ intellectual property, nor can it have its founders and employees working for the company. Still, the U.S. tech giant has had a few months to study its models and engineering expertise.

Meta has already agreed to undo the deal, with most of Manus’ operations reportedly running independently of the company. However, the Chinese startup still needs to break financially from the American tech giant by paying back the $2 billion the latter spent to purchase it. Even though Chinese companies are also investing massive amounts in AI tech, it’s still not easy to raise this amount of capital in such a short period.

Tencent, which owns the WeChat platform used by China’s 1.4 billion population for messaging, social networking, mobile payments, ride-hailing, food delivery, and more, believes that Manus would be an asset for the company. Aside from reaching an annual revenue of $500 million, its AI agent would also mesh well with the company's increasing AI focus. “Beyond foundation models, it has become increasingly evident that agentic AI represents a breakthrough use case,” Tencent president Martin Lau said in its May earnings call. “Our platform inherently has many benefits of hosting AI agents.”

SK hynix has completed the largest-ever foreign company IPO in U.S. history, raising $26.5 billion in its Nasdaq debut today, July 10. The South Korean memory giant sold 177.9 million American depositary receipts (ADRs) — a U.S.-listed stand-in for a foreign share — at $149 apiece, each representing a tenth of a Seoul-listed share. The offering was more than seven times oversubscribed and drew demand from more than 500 investment firms, according to Financial Times. Temporary Nasdaq trading is underway under the ticker SKHYV before regular-way trading begins as SKHY on Monday, July 13.

The offering was led by Bank of America, Citigroup, Goldman Sachs, and JPMorgan, with nine additional firms rounding out a 13-bank syndicate. Anchor demand came from heavyweight institutions including Baillie Gifford, Coatue Management, and Situational Awareness Partners, which together signaled interest in as much as $7 billion of stock, according to people familiar with the matter cited by Financial Times.

SK hynix is the world's leading maker of high-bandwidth memory (HBM), the vertically stacked DRAM that has become critical infrastructure for AI accelerators. The company has said it will steer the proceeds toward boosting its AI-memory manufacturing capacity. Confirmed build-outs include the first-phase fab at the massive Yongin semiconductor cluster, a new P&T7 advanced-packaging line in Cheongju, and EUV lithography equipment slated for delivery by the end of next year. Separately, SK hynix is constructing its first U.S. production site, a $4 billion advanced-packaging plant in West Lafayette, Indiana, targeted for completion around 2028. The facility is eligible for up to $458 million in CHIPS Act grants and up to $570 million in federal loans.

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SK hynix is seeing sensational growth thanks to the ongoing AI boom. The company is reportedly on track to post over 200 trillion won ($133 billion) in operating profit this year, a record-breaking figure that would see SK hynix employees earn around $400,000 each in bonuses. The company’s Seoul-listed stock is up roughly 220% year-to-date and has climbed more than sixfold over the past year.

In late June, SK hynix briefly surpassed Samsung as South Korea's most valuable company, closing at around 2,080 trillion won (about $1.35 trillion), a meteoric rise for a company that almost declared bankruptcy in 2001 and, more recently, recorded an annual operating loss of 7.73 trillion won in 2023. That rise doesn't seem like it will be slowing down any time soon. SK hynix has said its entire 2026 output of HBM, DRAM, and NAND is already sold out, with the crunch expected to extend into 2027.

Nanya Technology plans to increase its capital expenditure to more than TW$200 billion ($6.2 billion) in 2027, roughly four times its budget for this year, President Pei-Ing Lee said during an online briefing. The Taiwanese memory maker reported unaudited second-quarter revenue of T$82.55 billion, up 684% from 2025, and net income of T$50.19 billion, up 1,324%. Gross margin reached 79.5%, against a negative 20.6% during the same quarter of 2025. That single quarter's profit is 7.6 times what Nanya earned across the entirety of last year, and the quarter's revenue exceeds the company's entire 2025 sales.

Nanya spent T$13.2 billion on capex in 2023, T$16.1 billion in 2024, and T$13.4 billion in 2025, and has budgeted up to T$52 billion for 2026, per its Q1 investor presentation. Those four years together come to T$94.7 billion, less than half what Lee intends to spend in 2027 alone. Lee, however, admits that the 2027 figure is preliminary and hasn’t yet gone to the board, and that the new plant will absorb about T$480 billion at full capacity.

Nanya's average selling price climbed more than 70% quarter over quarter in Q1 2026, while its bit shipments fell by a mid-single-digit percentage, its own results deck shows. The company is targeting bit shipment growth in the teens for the full year, so almost all of the 684% revenue increase is due to price. Meanwhile, TrendForce projects a further 13% to 18% rise in conventional DRAM contract prices in Q3.

Roughly 70% of Nanya's shipments are DDR4 and low-power DDR4, Lee said at a January earnings conference, and DDR5 contributes about 10% of revenue. Nanya builds no high-bandwidth memory, and Lee has ruled out competing in HBM2, HBM3, HBM3E, or HBM4. A customized HBM part for edge AI, developed with Etron Technology, Piecemakers Technology, and Formosa Advanced Technologies, is targeted for the end of this year, however. Its 79.5% margin is close to a pure reading on conventional DRAM, and it sits within six points of the 85% consolidated gross margin Micron reported in its most recent 10-Q with HBM in the mix.

SanDisk, Kioxia, Solidigm, and Cisco paid T$78.72 billion for 10.19% of Nanya in a private placement completed in April, with SanDisk and Kioxia signing long-term DRAM supply agreements alongside the equity. Three of the four make SSDs and need DRAM for cache. Solidigm is a subsidiary of SK hynix, the world's second-largest DRAM maker, and it went to a supplier holding roughly 2% of the market to source it.

The first phase of Nanya's new fab in New Taipei City's Taishan District reaches 30,000 wafers per month in 2028 and expands to 45,000 later, Lee said Friday. The plant will run Nanya's 1B node, its second-generation 10nm-class process, to build DDR5, DDR4, and low-power DDR4, the company said during a March briefing. Lee said at that briefing that the most severe supply constraints run through the first half of 2027 and that the shortage persists into 2028. Samsung's P3 fab alone is expected to reach around 115,000 wafers per month by the end of this year.

Japanese chipmaker Rapidus will try to lure customers away from TSMC not only by offering a different kind of service, but also by offering its manufacturing services at lower prices, chief executive Atsuyoshi Koike announced this week. The company's plan to rival TSMC in terms of pricing appears on the surface as a risky move, as the company moves to develop leading-edge process technologies.

At present, Rapidus is looking at charging ¥3 million – ¥3.5 million ($18,550 - $21,635) per wafer processed using its 2nm-class fabrication process, which is significantly below TSMC's rumored quote of around $30,000 per N2 wafer, and is comparable to what Samsung is rumored to offer with its SF2 manufacturing technology, set at $20,000 per-wafer. Actual prices will depend on exchange rates, though Rapidus' general idea of offering significantly lower quotes than TSMC is immediately apparent.

Rapidus plans to start high-volume manufacturing (HVM) using its 2nm-class fabrication technology by the second half of 2027. The ramp of a new fab will take some time, so expect meaningful volumes from Rapidus to only be produced in 2028, when TSMC's N2 will no longer be its leading-edge node.

By the time Rapidus starts HVM at its IIM-1 in 2027, TSMC will have ramped production of chips using its performance-enhanced N2P manufacturing node, and the company will also absorb all the yield learning with gate-all-around the company will have with its N2 present at five fab modules. Furthermore, by the time Rapidus reaches meaningful volumes at IIM-1 in 2028, TSMC will have ramped up production using its advanced A16 fabrication process with Super Power Rail backside power delivery as well as a 3^rd-generation 2nm-class node named N2X.

In addition to the vast 2nm-capable capacity and process maturity that should be kept in mind when comparing Rapidus with TSMC, there is another factor to consider. One of TSMC's major advantages over its rivals is its Open Innovation Platform (OIP) ecosystem, which includes comprehensive electronic design automation tools, silicon-proven IPs, even for the latest nodes, a host of contract chip designers, and advanced packaging services not only from TSMC but also from its partners. For now, neither Rapidus nor Intel and Samsung Foundry can offer anything close to TSMC's OIP.

Given the advantages that TSMC will likely have over competitors with its 2nm-class fabrication technologies in 2028, lower pricing may be among the few ways to compete against the world's largest foundry. Rapidus' strategy of offering lower quotes while operating a single fab does not seem like the best way of earning money, but perhaps a certain way to lose it.

However, Rapidus may have another ace up its sleeve with single wafer processing across all process steps. The approach will greatly speed up the production cycle, which will be its indisputable advantage over other chipmakers, albeit at the cost of tool usage efficiency. Will lower quotes and shorter production cycles be enough for Rapidus to win customers from TSMC? Only time will tell.

Rapidus is reportedly negotiating with more than 60 potential customers, mainly overseas companies, which demonstrates the company's ambitions to become a viable rival to the global leader TSMC as well as contract chipmakers Intel Foundry and Samsung Foundry.

Researchers in Korea and Japan have presented two separate memory-integration proposals that aim to increase HBM (High-Bandwidth Memory) capacity and bandwidth without trapping more heat inside ever-taller DRAM (Dynamic Random Access Memory) stacks, one of the most pressing challenges facing future AI accelerators. Presented at the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits held in June, the two approaches — V-Die from a Korean research collaboration and MOSAIC from a University of Tokyo-led group — both explore the same broad idea of standing DRAM memory dies on their edges instead of stacking the memory dies only upward like conventional HBM.

The Korean proposal, called Vertical-Die (V-Die), was presented by researchers at the Ulsan National Institute of Science and Technology (UNIST). The design rotates custom DRAM dies upright, drops through-silicon vias to free die area for more memory cells, gives each die its own bottom-edge I/O, and runs liquid-cooling channels between adjacent dies. In simulations against an HBM4 system at equal capacity, the V-Die system reportedly achieved 540 tokens per second on a GPT-3-sized workload, compared to 296 tokens per second for HBM4.

The Japanese project, MOSAIC, takes a similar “sideways stack” idea but focuses on the practical difficulty of connecting so many vertical dies to a GPU or package substrate. Presented by University of Tokyo researchers, the MOSAIC work uses orthogonal die stacking and a contactless die-to-die interface, in which data is transferred through tiny inductive coils rather than requiring every signal pad to land perfectly on a physical contact. The researchers say the prototype interface achieved up to 4 Gbps per channel, while the memory structure could double HBM4-class capacity in a DRAM-on-GPU configuration.

Both projects aim to solve the growing problem of AI chips being held back by memory. Modern accelerators can perform enormous amounts of computation, but large, powerful models depend on moving huge amounts of data between memory and compute. This is why HBM has become one of the defining technologies of modern AI hardware.

The technology addresses the memory wall by stacking multiple DRAM dies vertically on a base die and placing that stack very close to the processor. Nvidia's Blackwell Ultra B300, for instance, carries up to 288GB of HBM3E memory, without which much of the silicon would sit idle waiting for data. The dies are connected via through-silicon vias (TSVs) — tiny vertical channels etched through the silicon and filled with metal.

The stack then communicates with the GPU over an extremely wide interface, often routed through a silicon interposer or an advanced package. This is the core reason HBM can deliver terabytes per second of bandwidth: it uses a very wide, very short data path instead of sending memory traffic across a motherboard, as with conventional DIMMs (Dual In-line Memory Modules), physical sticks of RAM used in computers.

However, that same structure creates several problems. While taller stacks add more capacity, they also make it harder to remove heat. Heat generated in the lower dies and at the high-speed interface must pass through layers of silicon, bonding materials, underfill, and package structures before it reaches a heat spreader. Furthermore, TSVs consume die area that could otherwise be used for memory cells, and as bandwidth rises, more routing and I/O place additional pressure on both signal integrity and packaging costs.

HBM4, the latest generation of HBM, addresses a number of these challenges. Meanwhile, companies such as SK hynix, Samsung, and Micron are racing to improve speed, capacity, base-die performance, and thermal management. SK hynix has already shown iHBM, which embeds cooling elements into the HBM interface area, and Samsung has shown an HBM5 mockup with Heat Path Block cooling to more directly extract heat from the stack. However, they all retain the same upward stacking structure.

This convention is what V-Die and MOSAIC are challenging. By standing DRAM dies upright, the researchers expose far more silicon surface area to the cooling path. In theory, this turns the memory stack into something closer to a heat-sink fin array, where heat can move laterally and escape more directly instead of being trapped in the middle of a thick vertical pile. It also opens the door to new connection schemes along the bottom or side of each die, rather than forcing every die to communicate through TSVs running vertically through the stack.

For V-Die, the key shift is removing TSVs from the memory dies and replacing them with bottom-edge connections. Each DRAM die gets its own I/O along the bottom edge and connects directly to the substrate, with links reportedly spaced every 20 microns. The team says this layout gives four times as many connections as HBM4 and cuts memory read time by 37%, although some signals must travel farther across the package to reach the processor.

Cooling is the other half of the V-Die argument. The proposal places microfluidic cooling channels between adjacent upright DRAM dies, allowing coolant to dissipate heat closer to its source. According to the researchers, this could keep the stack around 45°C, far below the 80°C-plus range associated with dense HBM systems. In a simulated 16-die stack matched to H100-class hardware on a GPT-3-scale model, V-Die hit 540 tokens per second, compared to HBM4's 296, and cut first-token latency by 32%, or about 24 milliseconds.

MOSAIC, meanwhile, is focused on making the sideways stack manufacturable. Because the dies are assembled flat and then turned on edge, even a few microns of die-thickness variation across dozens of dies can add up to an alignment miss where the signal pads no longer land. The Japanese team’s answer is a contactless interface based on inductive coupling. One side of the memory die carries oblong coils, while a corresponding set of coils sits on the substrate or mating chip. Current in one coil induces a signal in the other, allowing data to cross the small gap without a direct metal-to-metal signal contact. This eliminates the need for precise overlapping, giving the package greater tolerance for assembly variation. Power, which requires fewer, larger connections than data, can still be supplied via physical contacts on the sides of the memory cube.

The VLSI MOSAIC prototype achieved up to 4 Gbps per channel and demonstrated TSV-free 3D integration for a memory-on-GPU layout. The team says the approach can enable twice the memory capacity of HBM4 without significantly increasing peak temperature. A related bump-MOSAIC hardware demonstration at ECTC used 100-micron-pitch microbumps, achieved stacking alignment within 6 microns as verified by X-ray CT, and showed a configuration with three times the thermal conductivity of conventional stacking while adding up to 30% more memory capacity.

While the results look promising, neither V-Die nor MOSAIC is close to replacing commercial HBM. Neither is close to shipping. V-Die is still a proposed architecture, with a prototype in the works to validate its thermal and electrical behavior; MOSAIC has proof-of-principle hardware, but the researchers have yet to show it scales to commercial DRAM capacity, yield, cost, and reliability.

Still, any viable solution to the multifaceted AI memory problem is a welcome development. SoftBank and Intel’s Z-Angle Memory (ZAM) and NEO Semiconductor’s 3D X-DRAM — both still in development — aim to solve the constraints of conventional memory. Meanwhile, the overall market is already feeling the squeeze on price and availability, even as memory makers divert capacity toward the more lucrative AI HBM and server products, driving consumer RAM prices even higher.

The Chat Control 1.0 law that enables warrantless mass scanning of digital communications has been voted against multiple times by the EU Parliament. And yet, just like a movie zombie, it keeps getting resurrected by various legal sleight-of-hand moves. Yesterday, one of those tricks worked, as Chat Control 1.0 passed (or rather, was not rejected) in a forced re-vote that required an absolute majority (50% + 1) for active refusal. This brings back the law until 2028, and sets a different stage for September's upcoming discussion on Chat Control 2.0.

After the impending publication in the EU Official Journal, online direct-communication platforms will be allowed to mass-scan their users' data without the need for a warrant, under the guise of looking for child sexual abuse material (CSAM).

The scanning is not mandatory, but big tech firms will have a legal mechanism to rifle through user data. EU firms have historically refrained from doing so, presenting privacy and data sovereignty as selling points, but the legal door is nevertheless now officially open.

The obvious platforms where monitoring can now take place will be e-mail and chat services. Immediate examples include Gmail, iCloud, Hotmail, Discord, Instagram, Slack, Teams, Snapchat, Xbox, and Google Chat.

Although the law's scope is for "interpersonal communications services," the legal mechanism might hypothetically extend to some gray areas like Google Drive, where sending someone a link to a cloud file could be within the scope of the law.

It's worth noting that "direct communication" isn't restricted to one-to-one chats, as it includes group chats; just not public or undirected communications. Additionally, EU law enforcement is still beholden to the same warrant requirement as before — Chat Control 1.0 does not grant a blank pass to authorities to mass-scan user data, or request companies to do so without a targeted warrant.

Thanks to two amendments in yesterday's vote, end-to-end-encrypted (E2EE) communications means (ex: WhatsApp) stay exempt. That means that for now, Chat Control 1.0 isn't a commandment to break encryption, something that has been regularly suggested by lawmakers around the world.

It's as good a time as any to remind people that Instagram messages are no longer E2EE as of May, and that although WhatsApp's messages are encrypted, the service leaks out every single bit of metadata about them — sender, recipient, time, size, etc. As always, Signal is recommended as a privacy-focused communications app.

This latest development in the EU parliament is eliciting widespread public outcry due to the nature of the law itself, but also due to the manner in which it happened. Critics and opponents of the rule are suggesting this move is unprecedented.

Chat Control 1.0 has already been shot down repeatedly, most recently in March. However, European Parliament President Roberta Metsola forced a second reading of the law, and invoked Rule 163's "urgent procedure" mechanism. This had many effects, including bringing up a law that was voted against for discussion yet again; turning the decision into a denial vote (vote-to-deny, not vote-to-pass); exploiting the second-reading requirement that demands an absolute majority vote (50% + 1); and letting the President herself set the schedule. Metsola scheduled the second reading to the very last day before the European Parliament summer recess.

The result was that out of 720 representatives, only 607 actually cast a vote. Of those, 315 (over half) voted against Chat Control 1.0. That figure did not meet the supermajority threshold of 361, which was calculated against a full chamber.

Opponents to Chat Control have posted resources at the Fight Chat Control website, including a breakdown of member-state and individual representative voting positions and contact information.

Micron has said it will invest up to $3 billion in the U.S. semiconductor supply chain, with $500 million of that going to GlobalWafers as strategic financing for its 300 mm raw silicon wafer plant in Sherman, Texas, alongside a 10-year agreement giving Micron access to that plant's wafer output. In a separate announcement, the memory maker raised its planned U.S. spending to more than $250 billion through 2035, up from $200 billion, and confirmed the first concrete pour at its Clay, New York campus more than a quarter ahead of schedule.

Sherman is the sole operating facility in the U.S. capable of producing advanced 300 mm raw silicon wafers, the substrate on which every leading-edge DRAM, NAND, and logic die is built. GlobalWafers opened the plant in May last year and holds a $406 million CHIPS Act award covering the site and a silicon-on-insulator facility in St. Peters, Missouri. The 142-acre campus is designed for up to six phases, one of which is running. Micron's other American sites draw their wafers from Japan, Taiwan, Germany, and South Korea; Shin-Etsu, SUMCO, GlobalWafers, Siltronic, and SK Siltron together control the overwhelming majority of global 300 mm supply, making raw silicon the most concentrated layer in the chip space.

Doris Hsu, chairperson and CEO of GlobalWafers, set out her terms for building phase two at Sherman during the plant's opening last year, telling Reuters the company needed profitability at the first two phases, customers willing to sign long-term contracts, reasonable pricing, prepayments, and government support. Thursday's announcement supplies most of that list in a single transaction.

Wafer suppliers spent the 2023-2024 downcycle protecting margins rather than adding capacity, and SUMCO is winding down 200mm production at Miyazaki this year while holding the line on new 300mm expansion. Customers, not suppliers, are therefore now underwriting the capacity. The last time the industry did this, during the 2017-2018 megacycle, chipmakers signed prepaid long-term agreements that turned into liabilities when pricing rolled over.

Silicon wafer shipments reached 3,275 million square inches in Q1 2026, up 13.1% year over year, with SEMI.org attributing the growth to AI data center demand across advanced logic, memory, and power devices. Micron's first new Idaho fab, ID1, is expected to begin wafer output in mid-2027, and production at Clay isn't expected until around 2030. The company began making 1-alpha DRAM at its Manassas, Virginia fab in May.

Micron told investors last December that it can serve only half to two-thirds of customer demand, and nothing announced Thursday changes the supply position of DRAM this year or next.

Samsung is reportedly sampling its dedicated AI processor for next-generation AI PCs with leading PC makers, such as HP and Lenovo. The chip, codenamed Gaia, was developed by the company's System LSI business unit, and it is designed to offload AI-related workloads from the CPU and GPU, reports Chosun.

Samsung's Gaia is designed to accelerate generative AI workloads on PCs and is made using the company's 4nm-class fabrication process. The chip, which is essentially a neural processing unit (NPU), is currently being evaluated by HP in the U.S. and Lenovo in China to verify its performance and evaluate whether it makes sense to integrate Gaia into their systems due in late 2027 or early 2028.

The report does not detail how Gaia differs from NPUs that are integrated into AMD's Ryzen, Intel's Core, or Qualcomm's Snapdragon X processors as well as whether it can offer significant performance advantages. Meanwhile, the report implies that the NPU (or perhaps its derivatives based on the same architecture) could be used for Samsung's next-generation implementations of its processing-in-memory (PIM) technology.

Samsung's original PIM was designed to embed compute logic directly within the HBM memory array and reduce data movement between HBM memory modules and host processors. PIM was aimed to accelerate select workloads, but did not take off because AI and HPC GPUs became very efficient and were supported by mature ecosystems, unlike PIM.

Perhaps if Samsung's upcoming Gaia NPU gains support from hardware makers and ecosystem partners, then this will give a boost to Samsung's next-generation PIM implementation as well. However, standalone NPUs and PIM are so fundamentally different that we can barely imagine that they can share a common architecture. Yet, PIM logic can be a subset of an NPU in terms of supported instructions and data formats and they can certainly share a common software framework.

One of the interesting things to note about Gaia is that it was reportedly developed by Samsung's LSI division, the same business unit at the company that is responsible for Exynos processors, automotive solutions, connectivity chips, ISPs, DSPs, display drivers, and image sensors. Given the multi-faceted nature of Samsung's LSI unit, as well as its strategic importance for the company, Samsung must be pinning some hopes on Gaia.

We have contacted Samsung and asked for a comment about the report, but we yet have to hear back from the company.